74F113DCQR [FAIRCHILD]
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14;
| 型号： | 74F113DCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14 触发器 |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised July 1999
74F113
Dual JK Negative Edge-Triggered Flip-Flop
transferred to the outputs on the falling edge of the clock
pulse.
General Description
The 74F113 offers individual J, K, Set and Clock inputs.
When the clock goes HIGH the inputs are enabled and
data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is HIGH and the flip-
flop will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is
Asynchronous input:
LOW input to SD sets Q to HIGH level
Set is independent of clock
Ordering Code:
Order Number Package Number
Package Description
74F113SC
74F113SJ
74F113PC
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009473
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
J1, J2, K1, K2
CP1, CP2
Data Inputs
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
−1 mA/20 mA
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
1.0/4.0
S
D1, SD2
1.0/5.0
Q1, Q2, Q1, Q2 Outputs
50/33.3
Truth Table
Inputs
CP
Outputs
SD
J
K
Q
Q
L
X
X
h
l
X
h
h
l
H
L
H
H
H
H
Q0
L
Q0
H
h
l
H
L
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage level
]
= HIGH-to-LOW Clock Transition
X = Immaterial
(Q ) = Before HIGH-to-LOW Transition of Clock
Q
0
0
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to +7.0V
−30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IIN = −18 mA
VIL
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
VCD
VOH
−1.2
Min
Min
10% VCC
5% VCC
2.5
2.7
IOH = −1 mA
IOH = −1 mA
VOL
Output LOW
10% VCC
0.5
V
Min
IOL = 20 mA
Voltage
IIH
Input HIGH
5.0
7.0
50
µA
µA
µA
V
Max
Max
Max
0.0
VIN = 2.7V
VIN = 7.0V
Current
IBVI
ICEX
VID
IOD
IIL
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
V
OUT = VCC
IID = 1.9 µA
4.75
All Other Pins Grounded
Output Leakage
Circuit Current
Input LOW Current
VIOD = 150 mV
3.75
µA
0.0
All Other Pins Grounded
VIN = 0.5V (Jn, Kn)
VIN = 0.5V (CPn)
−0.6
−2.4
−3.0
50
mA
Max
VIN = 0.5V (SDn
)
IOZH
IOZL
IOS
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
µA
µA
Max
Max
Max
Max
V
V
V
OUT = 2.7V
OUT = 0.5V
OUT = 0V
−50
−150
19
−60
mA
mA
ICC
12
3
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AC Electrical Characteristics
T
A = +25°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
Symbol
Parameter
Units
CL = 50 pF
CL = 50 pF
Min
85
Typ
105
4.0
Max
Min Max
fMAX
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
80
2.0
2.0
MHz
ns
Propagation Delay
2.0
2.0
6.0
6.0
7.0
7.0
4.0
CPn to Qn or Qn
Propagation Delay
2.0
2.0
4.5
4.5
6.5
6.5
2.0
2.0
7.5
7.5
ns
SDn to Qn or Qn
AC Operating Requirements
TA = +25°C
VCC = +5.0V
Min Max
TA = 0°C to +70°C
VCC = +5.0V
Symbol
Parameter
Units
Min
5.0
3.5
Max
tS(H)
Setup Time, HIGH or LOW
4.0
3.0
tS(L)
Jn or Kn to CPn
ns
tH(H)
tH(L)
Hold Time, HIGH or LOW
0
0
0
0
Jn or Kn to CPn
tW(H)
tW(L)
tW(L)
4.5
4.5
4.5
5.0
5.0
5.0
CPn Pulse Width
HIGH or LOW
ns
ns
SDn Pulse Width, LOW
tREC
SDn to CPn
4.0
5.0
ns
Recovery Time
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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