74F114 [FAIRCHILD]
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears; 双JK负边沿触发触发器与普通时钟并清除
| 型号： | 74F114 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears |
| 文件： | 总6页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
General Description
The 74F114 contains two high-speed JK flip-flops with
common Clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of Clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
prevents clocking and forces Q or Q HIGH, respectively.
Ordering Code:
Order Number Package Number
Package Description
74F114SC
74F114PC
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009474
www.fairchildsemi.com
Unit Loading/Fan Out
U.L.
Input IIH/IIL
Pin Names
Description
HIGH/LOW
Output IOH/IOL
J1, J2, K1, K2
CP
Data Inputs
1.0/1.0
1.0/8.0
1.0/10.0
1.0/5.0
50/33.3
20 µA/−0.6 mA
20 µA/−4.8 mA
20 µA/−6.0 mA
20 µA/−3.0 mA
−1 mA/20 mA
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
CD
SD1, SD2
Q1, Q2, Q1, Q2 Outputs
Truth Table
Inputs
CP
Outputs
SD
CD
J
K
Q
Q
L
H
L
H
L
X
X
X
X
X
X
h
l
X
X
X
h
h
l
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
Q0
L
Q0
H
h
l
H
L
l
Q0
Q0
H (h) = HIGH Voltage Level
L (h) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q
(Q ) = Before HIGH-to-LOW Transition of Clock
0
0
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(one half shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
IL
−1.2
Min
Min
I
I
I
I
= −18 mA
CD
OH
IN
10% V
5% V
2.5
2.7
= −1 mA
= −1 mA
= 20 mA
CC
CC
CC
OH
OH
OL
V
Output LOW
10% V
0.5
V
Min
OL
Voltage
I
Input HIGH
IH
5.0
7.0
50
µA
µA
µA
V
Max
Max
Max
0.0
V
V
V
= 2.7V
= 7.0V
IN
Current
I
Input HIGH Current
Breakdown Test
Output High
BVI
IN
I
CEX
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
I
= 1.9 µA
ID
ID
4.75
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input LOW Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
−0.6
−3.0
V
V
V
= 0.5V (J , K )
n n
IL
IN
IN
IN
= 0.5V (S
)
Dn
mA
Max
−4.8
−6.0
= 0.5V (CP)
= 0.5V (C
V
V
V
V
)
Dn
IN
I
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
−150
19.0
19.0
mA
mA
mA
Max
Max
Max
= 0V
OUT
OS
I
12.0
12.0
= HIGH
= LOW
CCH
O
O
I
CCL
3
www.fairchildsemi.com
AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
75
Typ
95
Max
Min
70
Max
f
Maximum Clock Frequency
MHz
ns
MAX
t
Propagation Delay
CP to Q or Q
3.0
3.0
5.0
5.5
6.5
7.5
3.0
3.0
7.5
8.5
PLH
t
PHL
n
n
t
Propagation Delay
or S to Q or Q
n
3.0
3.0
4.5
4.5
6.5
6.5
3.0
3.0
7.5
7.5
PLH
ns
t
C
PHL
Dn
Dn
n
AC Operating Requirements
T
= +25°C
T = 0°C to +70°C
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
CC
Units
CC
Min
4.0
3.0
Max
Min
5.0
3.5
Max
t (H)
Setup Time, HIGH or LOW
or K to CP
S
t (L)
S
J
n
n
ns
t (H)
H
Hold Time, HIGH or LOW
or K to CP
0
0
0
0
t (L)
H
J
n
n
t
t
t
(H)
(L)
(L)
4.5
4.5
4.5
5.0
5.0
5.0
W
W
W
CP Pulse Width
HIGH or LOW
ns
ns
C
or S Pulse Width,
Dn
Dn
LOW
t
Recovery Time
4.0
5.0
ns
REC
S
, C , to CP
Dn
Dn
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
6
相关型号：
74F114D
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14
YAGEO
74F114D-T
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDSO14
YAGEO
74F114DC
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14
FAIRCHILD
74F114DC
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14
ROCHESTER
74F114DCQR
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14
FAIRCHILD
74F114L1C
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, LCC-20
FAIRCHILD
74F114L1CQR
J-K Flip-Flop, F/FAST Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, LCC-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明