74F161ADCQR [FAIRCHILD]
Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, CDIP16, CERAMIC, DIP-16;
| 型号： | 74F161ADCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, CDIP16, CERAMIC, DIP-16 计数器 |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised September 2000
74F161A • 74F163A
Synchronous Presettable Binary Counter
General Description
Features
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count frequency of 120 MHz
The 74F161A and 74F163A are high-speed synchronous
modulo-16 binary counters. They are synchronously pre-
settable for application in programmable dividers and have
two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multi-stage
counters. The 74F161A has an asynchronous Master-
Reset input that overrides all other inputs and forces the
outputs LOW. The 74F163A has a Synchronous Reset
input that overrides counting and parallel loading and
allows the outputs to be simultaneously reset on the rising
edge of the clock. The 74F161A and 74F163A are high-
speed versions of the 74F161 and 74F163.
Ordering Code:
Order Number Package Number
Package Description
74F161ASC
74F161ASJ
74F161APC
74F163ASC
74F163ASJ
74F163APC
M16A
M16D
N16E
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F161A
74F163A
© 2000 Fairchild Semiconductor Corporation
DS009486
www.fairchildsemi.com
Logic Symbols
74F161A
74F163A
IEEE/IEC
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
CEP
CET
CP
Count Enable Parallel Input
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
−1 mA/20 mA
−1 mA/20 mA
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
MR (74F161A) Asynchronous Master Reset Input (Active LOW)
SR (74F163A) Synchronous Reset Input (Active LOW)
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Q0–Q3
TC
Terminal Count Output
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2
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous reset (74F161A), synchronous reset
(74F163A), parallel load, count-up and hold. Five control
inputs—Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-
lel (CEP) and Count Enable Trickle (CET)—determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchro-
nously forces all outputs LOW. A LOW signal on SR over-
rides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchro-
nous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
State Diagram
Action on the Rising
Clock Edge (
Reset (Clear)
SR
(Note 1)
CE
P
PE CET
)
L
X
L
X
X
H
L
X
X
H
X
L
H
H
H
H
Load (Pn→Qn)
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: For 74F163A only
Block Diagram
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
VCD
VOH
−1.2
Min
Min
I
IN = −18 mA
10% VCC
5% VCC
2.5
2.7
V
V
VOL
Output LOW
Voltage
10% VCC
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
OL = 20 mA
IIH
Input HIGH
µA
µA
µA
V
V
V
V
IN = 2.7V
IN = 7.0V
OUT = VCC
Current
IBVI
ICEX
VID
IOD
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
I
ID = 1.9 µA
All Other Pins Grounded
IOD = 150 mV
All Other Pins Grounded
4.75
Output Leakage
Circuit Current
V
3.75
µA
0.0
IIL
Input LOW Current
−0.6
−1.2
−150
55
mA
mA
mA
mA
Max
Max
Max
Max
VIN = 0.5V (CEP, CP, MR, P0–P3)
VIN = 0.5V (CET, PE, SR)
VOUT = 0V
IOS
ICC
Output Short-Circuit Current
Power Supply Current
−60
37
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4
AC Electrical Characteristics
TA = +25°C
T
A = −55°C to +125°C
TA = 0°C to +70°C
V
CC = +5.0V
V
CC = +5.0V
L = 50 pF
Max
V
CC = +5.0V
L = 50 pF
Max
Symbol
Parameter
Units
C
L = 50 pF
C
C
Min
100
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
Typ
120
5.5
Max
Min
75
Min
90
fMAX
Maximum Count Frequency
Propagation Delay
CP to Qn (PE Input HIGH)
Propagation Delay
CP to Qn (PE Input LOW)
Propagation Delay
CP to TC
MHz
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
7.5
10.0
8.5
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
9.0
11.5
10.0
10.0
16.5
15.5
9.0
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
8.5
11.0
9.5
7.5
6.0
6.0
8.5
9.5
10.0
10.0
4.5
14.0
14.0
7.5
15.0
15.0
8.5
ns
ns
ns
ns
Propagation Delay
CET to TC
4.5
7.5
9.0
8.5
Propagation Delay
MR to Qn (74F161A)
Propagation Delay
MR to TC (74F161A)
5.5
4.5
9.0
8.0
12.0
10.5
5.5
4.5
14.0
12.5
5.5
4.5
13.0
11.5
tPHL
AC Operating Requirements
T
A = +25°C
T
A = −55°C to +125°C
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
VCC = +5.0V
VCC = +5.0V
V
Units
Min
5.0
5.0
2.0
2.0
Max
Min
5.5
5.5
2.5
2.5
Max
Min
5.0
5.0
2.0
2.0
tS(H)
Setup Time, HIGH or LOW
Pn to CP
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
ns
Hold Time, HIGH or LOW
Pn to CP
Setup Time, HIGH or LOW
PE or SR to CP
11.0
8.5
2.0
0
13.5
10.5
3.6
0
11.5
9.5
2.0
0
ns
ns
Hold Time, HIGH or LOW
PE or SR to CP
t
H(L)
tS(H)
tS(L)
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width (Load)
HIGH or LOW
11.0
5.0
0
13.0
6.0
0
11.5
5.0
0
t
H(H)
tH(L)
W(H)
0
0
0
t
5.0
5.0
4.0
6.0
5.0
5.0
5.0
8.0
5.0
5.0
4.0
7.0
ns
ns
tW(L)
tW(H)
tW(L)
Clock Pulse Width (Count)
HIGH or LOW
tW(L)
MR Pulse Width, LOW
(74F161A)
5.0
6.0
5.0
6.0
5.0
6.0
ns
ns
tREC
Recovery Time
MR to CP (74F161A)
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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