74F164A [FAIRCHILD]
Serial-In, Parallel-Out Shift Register; 串行输入，并行输出移位寄存器
| 型号： | 74F164A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Serial-In, Parallel-Out Shift Register |
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1989
Revised August 1999
74F164A
Serial-In, Parallel-Out Shift Register
General Description
Features
The 74F164A is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered through a 2-input AND
gate synchronous with the LOW-to-HIGH transition of the
clock. The device features an asynchronous Master Reset
which clears the register, setting all outputs LOW indepen-
dent of the clock. The 74F164A is a faster version of the
74F164.
■ Typical shift frequency of 90 MHz
■ Asynchronous Master Reset
■ Gated serial data input
■ Fully synchronous data transfers
■ 74F164A is a faster version of the 74F164
Ordering Code:
Order Number Package Number
Package Description
74F164ASC
74F164ASJ
74F164APC
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS010613
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
A, B
CP
Data Inputs
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
1.0/1.0
1.0/1.0
MR
Q0–Q7
50/33.3
Functional Description
Mode Select Table
The 74F164A is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
HIGH Enable for data entry through the other input. An
unused input must be tied HIGH.
Operating
Inputs
Outputs
Q0
Q1–Q7
Mode
MR
L
A
X
l
B
X
l
Reset (Clear)
L
L
L
L
H
L-L
H
q0–q6
q0–q6
q0–q6
q0–q6
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the log-
Shift
H
l
h
l
H
h
h
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
H
h
H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Immaterial
q
= Lower case letters indicate the state of the referenced input or output
n
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 1)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 1)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
= −18 mA
CD
OH
IN
10% V
5% V
2.5
2.7
= −1 mA
= −1 mA
CC
OH
OH
V
V
Voltage
CC
V
Output LOW
OL
10% V
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
= 20 mA
= 2.7V
= 7.0V
CC
OL
Voltage
I
Input HIGH
IH
µA
µA
µA
V
V
V
V
IN
Current
I
Input HIGH Current
Breakdown Test
Output HIGH
BVI
IN
I
CEX
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
I
= 1.9 µA
ID
ID
4.75
All other pins grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
OD
3.75
µA
0.0
All other pins grounded
I
−0.6
−150
55
mA
mA
mA
Max
Max
Max
V
V
= 0.5V
IL
IN
I
−60
= 0V
OUT
OS
I
35
CP = HIGH
CC
MR = GND, A, B = GND
3
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AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= 5.0V
V = 5.0V
CC
CC
CC
Symbol
Parameter
Units
C
C
= 50 pF
C = 50 pF
L
L
L
Min
80
Typ
120
4.8
Max
Min
60
Max
Min
80
Max
f
Maximum Clock Frequency
Propagation Delay
MHz
ns
MAX
t
3.0
3.5
7.5
8.0
2.5
3.0
9.0
8.5
3.0
3.5
7.5
8.0
PLH
t
CP to Q
5.0
PHL
n
t
Propagation Delay
MR to Q
PHL
5.0
7.0
10.0
4.0
12.5
5.0
10.5
ns
n
AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= 5.0V
V = 5.0V
CC
Units
CC
CC
Min
4.5
4.0
1.0
1.0
4.0
7.0
Max
Min
5.5
4.0
1.0
1.0
4.0
7.0
Max
Min
4.5
4.0
1.0
1.0
4.0
7.0
Max
t (H)
Setup Time, HIGH or LOW
S
t (L)
A or B to CP
S
ns
t (H)
Hold Time, HIGH or LOW
A or B to CP
H
t (L)
H
t
t
t
(H)
(L)
(L)
CP Pulse Width
HIGH or LOW
W
W
ns
ns
ns
4.0
5.0
4.0
MR Pulse Width, LOW
Recovery Time
W
t
REC
5.0
6.5
5.0
MR to CP
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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