74F257A [FAIRCHILD]
Quad 2-Input Multiplexer with 3-STATE Outputs; 四2输入多路复用器与3态输出
| 型号： | 74F257A |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input Multiplexer with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F257A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
Features
The 74F257A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a Common Data Select input. The four outputs
present the selected data in true (non-inverted) form. The
outputs may be switched to a high impedance state with a
HIGH on the common Output Enable (OE) input, allowing
the outputs to interface directly with bus-oriented systems.
■ Multiplexer expansion by tying outputs together
■ Non-inverting 3-STATE outputs
■ Input clamp diodes limit high-speed termination effects
Ordering Code:
Order Number Package Number
Package Description
74F257ASC
74F257ASJ
74F257APC
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009507
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
S
Common Data Select Input
20 µA/−0.6 mA
20 µA/−0.6 mA
3-STATE Output Enable Input (Active LOW)
1.0/1.0
OE
I0a–I0d
I1a–I1d
Za–Zd
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Multiplexer Outputs
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
150/40 (33.3) −3 mA/24 mA (20 mA)
Truth Table
Functional Description
The 74F257A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
input is LOW, the I0x inputs are selected and when Select
Output
Enable
Select
Data
Output
Z
Input
S
Inputs
OE
I0
I1
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (non-
inverted) form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
The logic equation for the outputs is shown below:
H
L
L
L
L
X
H
H
L
X
X
X
L
X
L
Z
L
H
X
X
H
L
Zn = OE • (In• S + Ion • S)
L
H
H
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs
are tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed
the maximum ratings. Designers should ensure the Output
Enable signals to 3-STATE devices whose outputs are tied
together are designed so there is no overlap.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
I
I
= −18 mA
CD
OH
IN
10% V
10% V
5% V
2.5
2.4
2.7
2.7
= −1 mA
= −3 mA
= −1 mA
= −3 mA
CC
CC
CC
CC
CC
OH
OH
OH
OH
Voltage
V
5% V
V
Output LOW
10% V
OL
0.5
5.0
7.0
50
V
Min
Max
Max
Max
0.0
I
= 24 mA
= 2.7V
= 7.0V
OL
Voltage
I
Input HIGH
IH
µA
µA
µA
V
V
V
V
IN
Current
I
Input HIGH Current
Breakdown Test
Output HIGH
BVI
IN
I
CEX
= V
OUT
CC
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
−0.6
50
mA
µA
Max
Max
Max
Max
0.0V
Max
Max
Max
V
V
V
V
V
V
V
V
= 0.5V
IL
IN
I
= 2.7V
= 0.5V
= 0V
OZH
OUT
OUT
OUT
OUT
I
−50
−150
500
15
µA
OZL
I
−60
mA
µA
OS
I
= 5.25V
ZZ
I
9.0
14.5
15
mA
mA
mA
= HIGH
CCH
O
O
O
I
22
= LOW
CCL
I
23
= HIGH Z
CCZ
3
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AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= 5.0V
V
= 5.0V
V = 5.0V
CC
CC
CC
Symbol
Parameter
Units
C
= 50 pF
C
= 50 pF
C = 50 pF
L
L
L
Min
2.5
2.0
4.0
2.5
2.0
2.5
2.0
2.0
Typ
4.5
4.2
5.0
6.5
5.9
5.5
4.3
4.5
Max
5.5
5.5
9.5
7.0
6.0
7.0
6.0
6.0
Min
2.0
1.5
3.5
2.5
2.0
2.5
2.0
2.0
Max
Min
2.0
2.0
3.5
2.5
2.0
2.5
2.0
2.0
Max
t
Propagation Delay
I to Z
n
7.0
7.0
11.5
9.0
8.0
9.0
7.0
8.5
6.0
6.0
10.5
8.0
7.0
8.0
7.0
7.0
PLH
ns
ns
t
PHL
n
t
Propagation Delay
S to Z
PLH
t
PHL
n
t
Output Enable Time
PZH
t
PZL
ns
t
Output Disable Time
PHZ
t
PLZ
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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