74F382SC [FAIRCHILD]
4-Bit Arithmetic Logic Unit; 4位算术逻辑单元
| 型号： | 74F382SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4-Bit Arithmetic Logic Unit |
| 文件： | 总8页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1988
Revised August 1999
74F382
4-Bit Arithmetic Logic Unit
General Description
Features
The 74F382 performs three arithmetic and three logic oper-
ations on two 4-bit words, A and B. Two additional Select
input codes force the Function outputs LOW or HIGH. An
Overflow output is provided for convenience in twos com-
plement arithmetic. A Carry output is provided for ripple
expansion. For high-speed expansion using a Carry Looka-
head Generator, refer to the 74F381 data sheet.
■ Performs six arithmetic and logic functions
■ Selectable LOW (clear) and HIGH (preset) functions
■ LOW input loading minimizes drive requirements
■ Carry output for ripple expansion
■ Overflow output for twos complement arithmetic
Ordering Code:
Order Number Package Number
Package Description
74F382SC
74F382SJ
74F382PC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009529
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/4.0
A0–A3
B0–B3
S0–S2
Cn
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
20 µA/−2.4 mA
20 µA/−2.4 mA
20 µA/−0.6 mA
20 µA/−3.0 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
1.0/4.0
1.0/1.0
1.0/5.0
Cn + 4
OVR
Carry Output
50/33.3
50/33.3
50/33.3
Overflow Output
Function Outputs
F0–F3
Functional Description
Function Select Table
Signals applied to the Select inputs S0–S2 determine the
Select
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the Cn input of the least significant package.
Operation
Clear
S0
S1
S2
L
H
L
L
L
L
L
B Minus A
A Minus B
A Plus B
H
H
L
L
H
L
L
H
H
H
H
A
B
Ripple expansion is illustrated in Figure 2. The overflow
output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a
H
L
L
A + B
AB
H
H
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in
Figure 1.
H
Preset
H = HIGH Voltage Level
L = LOW Voltage Level
Toward
F
Output
Path Segment
Cn + 4, OVR
A1 or B1 to Cn + 4
Cn to Cn + 4
6.5 ns
6.3 ns
6.3 ns
8.1 ns
—
6.5 ns
6.3 ns
6.3 ns
—
Cn to Cn + 4
Cn to F
Cn to Cn + 4, OVR
Total Delay
8.0 ns
27.1 ns
27.2 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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2
Truth Table
Inputs
Outputs
F3
S0
S1
S2
Cn
An
Bn
F0
F1
F2
Cn + 4
Function
OVR
H
H
L
CLEAR
L
L
L
L
H
L
X
X
L
X
X
L
L
L
L
L
L
L
L
L
H
H
L
B MINUS A
A MINUS B
A PLUS B
H
L
H
H
L
H
L
H
H
L
H
H
L
H
H
L
L
L
H
L
L
H
L
L
H
H
L
L
L
L
H
L
H
L
H
L
H
L
H
L
L
L
H
H
H
H
L
L
H
H
L
L
H
L
H
H
L
H
L
H
L
H
L
L
H
H
L
L
H
L
L
L
L
L
H
L
L
L
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
H
H
L
H
H
L
L
H
L
L
H
L
H
L
L
H
H
H
H
L
L
H
L
L
H
L
H
H
L
L
L
L
L
H
H
L
H
L
H
L
H
L
L
H
H
L
H
L
L
H
L
L
L
L
L
L
L
L
H
L
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
L
L
L
H
H
L
L
L
L
H
L
L
H
L
H
H
H
H
X
X
L
H
L
L
L
H
L
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
L
A
B
L
H
L
L
L
H
H
H
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
H
L
L
L
H
H
H
L
L
L
X
H
X
X
X
L
H
L
H
H
L
H
H
L
H
L
H
L
H
L
H
L
A + B
L
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
L
L
L
H
X
X
X
L
H
H
L
H
H
L
AB
H
H
L
H
L
L
L
L
L
H
H
H
L
L
L
L
L
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
L
H
L
H
L
PRESET
H
L
H
L
L
L
H
H
H
L
L
H
H
L
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
3
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Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
V
CC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to +7.0V
−30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics over Operating Temperature Range unless otherwise specified
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
0.8
IL
−1.2
Min
Min
I
I
I
= −18 mA
CD
OH
IN
10% V
5% V
2.5
2.7
= −1 mA
= −1 mA
CC
OH
OH
V
V
CC
V
Output LOW
OL
10% V
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
= 20 mA
= 2.7V
= 7.0V
CC
OL
Voltage
I
Input HIGH
IH
µA
µA
µA
V
V
V
V
IN
Current
I
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
BVI
IN
I
CEX
= V
OUT
CC
V
I
= 1.9 µA
ID
ID
4.75
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input LOW Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
−0.6
−2.4
−3.0
−150
81
V
V
V
V
= 0.5V (S – S )
0 2
IL
IN
mA
Max
= 0.5V (A – A , B – B )
0 3 0 3
IN
= 0.5V (C )
IN
n
I
Output Short-Circuit Current
Power Supply Current
−60
mA
mA
Max
Max
= 0V
OUT
OS
I
54
CC
5
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AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
3.0
2.5
4.0
3.0
6.5
4.0
3.5
3.5
7.0
5.0
2.5
3.5
3.5
2.5
7.0
3.0
Typ
8.1
Max
12.0
8.0
Min
3.0
2.5
3.5
2.5
5.5
4.0
3.5
3.5
7.0
5.0
2.0
2.0
3.5
2.5
7.0
3.0
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
to F
13.0
9.0
PLH
ns
ns
ns
ns
ns
ns
ns
ns
C
5.7
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
n
i
Propagation Delay
Any A or B to Any F
Propagation Delay
10.4
8.2
15.0
11.0
20.5
15.0
8.5
17.0
12.0
21.5
17.5
11.0
10.5
17.5
14.5
9.0
11.0
8.2
S to F
i
i
Propagation Delay
A or B to C + 4
6.0
6.5
9.0
i
i
n
Propagation Delay
S to OVR or C
12.5
9.0
16.5
12.0
8.0
i
n + 4
Propagation Delay
to C
5.6
C
6.3
9.0
10.0
13.0
11.0
16.5
11.5
n
n + 4
Propagation Delay
to OVR
8.0
11.0
10.0
15.5
10.5
C
7.1
n
Propagation Delay
A or B to OVR
11.5
8.0
i
i
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
相关型号：
74F382SPCQR
Arithmetic Logic Unit, F/FAST Series, 4-Bit, TTL, PDIP20, SLIM, PLASTIC, DIP-20
FAIRCHILD
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