74F398 [FAIRCHILD]
Quad 2-Port Register; 四2端口寄存器
| 型号： | 74F398 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Port Register |
| 文件： | 总8页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F398 • 74F399
Quad 2-Port Register
General Description
Features
■ Select inputs from two data sources
■ Fully positive edge-triggered operation
■ Both true and complement outputs—74F398
The 74F398 and 74F399 are the logical equivalents of a
quad 2-input multiplexer feeding into four edge-triggered
flip-flops. A common Select input determines which of the
two 4-bit words is accepted. The selected data enters the
flip-flops on the rising edge of the clock. The 74F399 is the
16-pin version of the 74F398, with only the Q outputs of the
flip-flops available.
Ordering Code:
Order Number Package Number
Package Description
74F398SC
74F398PC
74F399SC
74F399SJ
74F399PC
M20B
N20A
M16A
M16D
N16E
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
74F398
74F399
© 1999 Fairchild Semiconductor Corporation
DS009533
www.fairchildsemi.com
Logic Symbols
74F398
74F398
74F399
74F399
IEEE/IEC
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
S
Common Select Input
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
CP
Clock Pulse Input (Active Rising Edge)
Data Inputs from Source 0
1.0/1.0
I0a–I0d
I1a–I1d
Qa–Qd
Qa–Qd
1.0/1.0
Data Inputs from Source 1
1.0/1.0
Register True Outputs
50/33.3
50/33.3
Register Complementary Outputs (74F398)
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2
Functional Description
Function Table
The 74F398 and 74F399 are high-speed quad 2-port regis-
ters. They select four bits of data from either of two sources
(Ports) under control of a common Select input (S). The
selected data is transferred to a 4-bit output register syn-
chronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-type output register is fully edge-
triggered. The Data inputs (I0x, I1x) and Select input (S)
Inputs
Outputs
S
I0
I1
Q
Q
(Note 1)
I
I
I
X
X
I
L
H
L
H
L
h
X
X
must be stable only a setup time prior to and hold time after
the LOW-to-HIGH transition of the Clock input for predict-
able operation. The 74F398 has both Q and Q outputs.
h
H
L
h
h
H
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
X = Immaterial
Note 1: 74F398 only
Logic Diagram
*F398 Only
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
twice the rated IOL(mA)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
ESD Last Passing Voltage
(Min)—74F399
4000V
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
Min
I
I
I
I
= −18 mA
CD
OH
IN
10% V
2.5
2.7
= −1 mA
= −1 mA
= 20 mA
CC
OH
OH
OL
V
V
Voltage
5% V
10% V
CC
V
Output LOW
0.5
OL
CC
Voltage
I
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
5.0
7.0
µA
µA
Max
Max
V
V
= 2.7V
= 7.0V
IH
IN
I
BVI
IN
I
CEX
50
µA
V
Max
0.0
V
= V
OUT CC
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
−0.6
−150
38
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
Max
Max
V
V
V
V
V
V
= 0.5V
IL
IN
I
−60
= 0V
OUT
OS
I
Power Supply Current (74F398)
Power Supply Current (74F398)
Power Supply Current (74F399)
Power Supply Current (74F399)
25
25
22
22
= HIGH
= LOW
= HIGH
= LOW
CCH
O
O
O
O
I
38
CCL
I
34
CCH
I
34
CCL
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4
AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
Typ
140
5.7
Max
Min
100
3.0
Max
f
t
Input Clock Frequency
100
MHz
ns
MAX
Propagation Delay
3.0
(Note 4)
7.5
9.0
8.5
PLH
t
CP to Q or Q
3.0
6.8
3.0
10.0
PHL
Note 4: 74F398 3.3 ns
AC Operating Requirements
T
= +25°C
T = 0°C to +70°C
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
Units
CC
CC
Min
3.0
3.0
1.0
1.0
7.5
7.5
7.5
7.5
0
Max
Min
3.0
3.0
1.0
1.0
8.5
8.5
8.5
8.5
0
Max
t (H)
Setup Time, HIGH or LOW
to CP
S
t (L)
I
n
S
ns
t (H)
Hold Time, HIGH or LOW
to CP
H
t (L)
I
n
H
t (H)
Setup Time, HIGH or LOW
S to CP (F398)
S
t (L)
S
t (H)
Setup Time, HIGH or LOW
S to CP (F399)
S
ns
ns
t (L)
S
t (H)
Hold Time, HIGH or LOW
S to CP
H
t (L)
0
0
H
t
t
(H)
(L)
CP Pulse Width
4.0
5.0
4.0
5.0
W
W
HIGH or LOW
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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