74F402PC [FAIRCHILD]
Serial Data Polynomial Generator/Checker; 串行数据多项式发生器/校验器
| 型号： | 74F402PC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Serial Data Polynomial Generator/Checker |
| 文件： | 总9页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F402
Serial Data Polynomial Generator/Checker
General Description
Features
The 74F402 expandable Serial Data Polynomial generator/
checker is an expandable version of the 74F401. It pro-
vides an advanced tool for the implementation of the most
widely used error detection scheme in serial digital han-
dling systems. A 4-bit control input selects one-of-six gen-
erator polynomials. The list of polynomials includes CRC-
16, CRC-CCITT and Ethernet , as well as three other
standard polynomials (56th order, 48th order, 32nd order).
Individual clear and preset inputs are provided for floppy
disk and other applications. The Error output indicates
whether or not a transmission error has occurred. The
CWG Control input inhibits feedback during check word
transmission. The 74F402 is compatible with FAST
devices and with all TTL families.
■ Guaranteed 30 MHz data rate
■ Six selectable polynomials
■ Other polynomials available
■ Separate preset and clear controls
■ Expandable
■ Automatic right justification
■ Error output open collector
■ Typical applications: Floppy and other disk storage sys-
tems Digital cassette and cartridge systems Data com-
munication systems
Ordering Code:
Order Number Package Number
Package Description
74F402PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
FAST is a registered trademark of Fairchild Semiconductor Corporation.
Ethernet is a registered trademark of Xerox Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009535
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Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/0.67
S0–S3
CWG
D/CW
D
Polynomial Select Inputs
Check Word Generate Input
Serial Data/Check Word
Data Input
20 µA/−0.4 mA
20 µA/−0.4 mA
1.0/0.67
285(100)/13.3(6.7)
1.0/0.67
−5.7 mA(−2 mA)/8 mA (4 mA)
20 µA/−0.4 mA
Error Output
(Note 1) /26.7(13.3)
(Note 1) /16 mA (8 mA)
ER
RO
CP
Register Output
Clock Pulse
285(100)/13.3(6.7)
1.0/0.67
−5.7 mA(−2 mA)/8 mA (4 mA)
20 µA/−0.4 mA
SEI
RFB
MR
Serial Expansion Input
Register Feedback
Master Reset
1.0/0.67
20 µA/−0.4 mA
1.0/0.67
20 µA/−0.4 mA
1.0/0.67
20 µA/−0.4 mA
Preset
1.0/0.67
20 µA/−0.4 mA
P
Note 1: Open Collector
Functional Description
The 74F402 Serial Data Polynomial Generator/Checker is
an expandable 16-bit programmable device which oper-
ates on serial data streams and provides a means of
detecting transmission errors. Cyclic encoding and decod-
ing schemes for error detection are based on polynomial
manipulation in modulo arithmetic. For encoding, the data
stream (message polynomial) is divided by a selected poly-
nomial. This division results in a remainder (or residue)
which is appended to the message as check bits. For error
checking, the bit stream containing both data and check
bits is divided by the same selected polynomial. If there are
no detectable errors, this division results in a zero remain-
der. Although it is possible to choose many generating
polynomials of a given degree, standards exist that specify
a small number of useful polynomials. The 74F402 imple-
ments the polynomials listed in Table 1 by applying the
appropriate logic levels to the select pins S0, S1, S2 and S3.
erate (CWG) must be held HIGH while the data is being
entered. After the last data bit is entered, the CWG is
brought LOW and the check bits are shifted out of the reg-
ister(s) and appended to the data bits (no external gating is
needed).
To check an incoming message for errors, both the data
and check bits are entered through the D Input with the
CWG Input held HIGH. The Error Output becomes valid
after the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP, with the exception of the
Ethernet polynomial (see Applications paragraph). If no
detectable errors have occurred during the data transmis-
sion, the resultant internal register bits are all LOW and the
Error Output (ER) is HIGH. If a detectable error has
occurred, ER is LOW. ER remains valid until the next LOW-
to-HIGH transition of CP or until the device has been pre-
set or reset.
The 74F402 consists of a 16-bit register, a Read Only
Memory (ROM) and associated control circuitry as shown
in the Block Diagram. The polynomial control code pre-
sented at inputs S0, S1, S2 and S3 is decoded by the ROM,
A HIGH on the Master Reset Input (MR) asynchronously
clears the entire register. A LOW on the Preset Input (P)
asynchronously sets the entire register with the exception
of:
selecting the desired polynomial or part of a polynomial by
establishing shift mode operation on the register with
Exclusive OR (XOR) gates at appropriate inputs. To gener-
ate the check bits, the data stream is entered via the Data
Inputs (D), using the LOW-to-HIGH transition of the Clock
Input (CP). This data is gated with the most significant
Register Output (RO) via the Register Feedback Input
(RFB), and controls the XOR gates. The Check Word Gen-
1. The Ethernet residue selection, in which the registers
containing the non-zero residue are cleared;
2. The 56th order polynomial, in which the 8 least signifi-
cant register bits of the least significant device are
cleared; and,
3. Register S = 0, in which all bits are cleared.
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2
TABLE 1.
Select Code
Hex
Polynomial
Remarks
S = 0
S3
S2
S1
S0
0
C
D
E
F
7
B
3
2
4
8
5
9
1
6
A
L
H
H
H
H
L
L
H
H
H
H
H
L
L
L
L
L
0
X32+X26+X23+X22+X16
X12+X11+X10+X8+X7+X5+X4+X2+X+1
X32+X31+X27+X26+X25+X19+X16
+
Ethernet
L
H
L
Polynomial
Ethernet
H
H
H
H
H
H
L
+
H
H
H
H
L
X15+X13+X12+X11+X9+X7+X6+X5+X4+X2+X+1
X16+X15+X2+1
Residue
CRC-16
H
L
X16+X12+X5+1
CRC-CCITT
L
X56+X55+X49+X45+X41
X39+X38+X37+X36+X31
+
+
L
L
56th
L
H
L
L
X22+X19+X17+X16+X15+X14+X12+X11+X9+
Order
H
L
L
L
X5+X+1
X48+X36+X35+
H
L
L
H
H
H
L
H
L
L
X23+X21
X15+X13+X8+X2+1
+
48th
L
L
Order
32nd
Order
L
H
L
H
H
X32+X23+X21
X11+X2+1
+
H
L
Block Diagram
3
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TABLE 2.
P0
P3
P2
P1
C2
C1
C0
Select Code
Polynomial
S = 0
0
C
D
E
F
7
B
3
2
4
8
5
9
1
6
A
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Ethernet
Polynomial
Ethernet
Residue
CRC-16
CRC-CCITT
56th
Order
48th
Order
32nd
Order
Applications
In addition to polynomial selection there are four other
capabilities provided for in the 74F402 ROM. The first is set
or clear selectability. The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW. This set or clear capability is done in four groups of 4
(see Table 2, P0–P3). The second ROM capability (C0) is in
This allows the user to choose a lower order polynomial
even if the system is configured for a higher order one.
The 74F402 expandable CRC generator checker contains
6 popular CRC polynomials, 2-16th Order, 2-32nd Order, 1-
48th Order and 1-56th Order. The application diagram
shows the 74F402 connected for a 56th Order polynomial.
Also shown are the input patterns for other polynomials.
When the 74F402 is used with a gated clock, disabling the
clock in a HIGH state will ensure no erroneous clocking
occurs when the clock is re-enabled. Preset and Master
Reset are asynchronous inputs presetting the register to S
or clearing to 1s respectively (note Ethernet residue and
determining the polarity of the check word. As is the case
with the Ethernet polynomial the check word can be
inverted when it is appended to the data stream or as is the
case with the other polynomials, the residue is appended
with no inversion. Thirdly, the ROM contains a bit (C1)
which is used to select the RFB input instead of the SEI
input to be fed into the LSB. This is used when the polyno-
mial selected is actually a residue (least significant) stored
in the ROM which indicates whether the selected location
is a polynomial or a residue. If the latter, then it inhibits the
RFB input.
56th Order select code 8, LSB, are exceptions to this).
To generate a CRC, the pattern for the selected polynomial
is applied to the S inputs, the register is preset or cleared
as required, clock is enabled, CWG is set HIGH, data is
applied to D input, output data is on D/CW. When the last
data bit has been entered, CWG is set LOW and the regis-
ter is clocked for n bits (where n is the order of the polyno-
mial). The clock may now be stopped if desired (holding
CWG LOW and clocking the register will output zeros from
D/CW after the residue has been shifted out).
As mentioned previously, upon a successful data transmis-
sion, the CRC register has a zero residue. There is an
exception to this, however, with respect to the Ethernet
polynomial. This polynomial, upon a successful data trans-
mission, has a non-zero residue in the CRC register (C7 04
DD 7B)16. In order to provide a no-error indication, two
To check a CRC, the pattern for the selected polynomial is
applied to the S inputs, the register is preset or cleared as
required, clock is enabled, CWG is set HIGH, the data
stream including the CRC is applied to D input. When the
last bit of the CRC has been entered, the ER output is
checked: HIGH = error free data, LOW = corrupt data. The
clock may now be stopped if desired.
ROM locations have been preloaded with the residue so
that by selecting these locations and clocking the device
one additional time, after the last check bit has been
entered, will result in zeroing the CRC register. In this man-
ner a no-error indication is achieved.
With the present mix of polynomials, the largest is 56th
order requiring four devices while the smallest is 16th order
requiring just one device. In order to accommodate multi-
plexing between high order polynomials (X 16th order) and
lower order polynomials, a location of all zeros is provided.
To implement polynomials of lower order than 56th, select
the number of packages required for the order of polyno-
mial and apply the pattern for the selected polynomial to
the S inputs (0000 on S inputs disables the package from
the feedback chain).
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4
5
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 3)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
= −18 mA
CD
OH
IN
10% V
5% V
2.4
2.7
= −5.7 mA (RO, D/CW)
= −5.7 mA (RO, D/CW)
CC
OH
OH
V
Voltage
CC
V
Output LOW
10% V
0.5
0.5
I
I
= 16 mA (ER)
OL
CC
CC
OL
OL
Voltage
10% V
= 8 mA (D/CW, RO)
I
I
I
Input HIGH
IH
5.0
7.0
50
µA
µA
µA
V
Max
Max
Max
0.0
V
V
V
= 2.7V
= 7.0V
IN
Current
Input HIGH Current
Breakdown Test
Output HIGH
BVI
IN
CEX
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
I
= 1.9 µA
ID
ID
4.75
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
I
−0.4
mA
mA
Max
Max
V = 0.5V
IN
IL
−20
−130
V
= 0V (D/CW, RO)
OS
OUT
I
Open Collector, Output
OFF Leakage Test
OHC
250
165
µA
Min
V
= V (ER)
CC
OUT
I
Power Supply Current
110
mA
Max
CC
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6
AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
30
Typ
45
Max
Min
30
Max
Min
30
Max
f
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
CP to D/CW
MHz
ns
MAX
8.5
15.0
18.0
13.5
14.0
26.0
14.5
19.0
23.0
17.0
18.0
33.0
18.5
7.5
9.5
7.0
7.0
26.5
26.5
26.0
22.5
38.5
23.5
7.5
9.5
7.0
7.0
21.0
25.0
19.0
20.0
35.0
20.5
PLH
PHL
PLH
PHL
PLH
PHL
10.5
8.0
Propagation Delay
CP to RO
ns
ns
ns
ns
8.0
Propagation Delay
15.5
8.5
14.0
7.5
14.0
7.5
CP to ER
t
t
t
Propagation Delay
P to D/CW
11.0
11.5
18.5
19.5
23.5
24.5
10.0
10.5
31.0
32.0
10.0
10.5
25.5
26.5
PLH
PHL
PLH
Propagation Delay
9.5
16.0
17.0
20.5
21.5
8.5
9.0
31.5
26.0
8.5
9.0
22.5
23.5
P to RO
t
Propagation Delay
PLH
10.0
ns
ns
ns
ns
ns
ns
ns
P to ER
t
t
t
Propagation Delay
MR to D/CW
10.5
11.0
18.0
19.0
23.0
24.0
9.5
29.0
28.5
9.5
25.5
26.0
PLH
PHL
PHL
10.0
10.0
Propagation Delay
MR to RO
9.0
15.5
28.0
19.5
35.5
8.0
23.5
39.0
8.0
21.5
37.5
t
Propagation Delay
PLH
16.5
14.5
14.5
MR to ER
t
t
t
t
t
t
Propagation Delay
D to D/CW
6.0
7.5
6.5
7.0
11.5
9.5
10.5
12.0
11.0
12.0
19.5
16.0
13.5
16.0
14.0
15.5
24.5
20.0
5.0
6.5
5.5
6.0
9.0
8.5
19.5
20.0
21.5
21.5
29.0
25.0
5.0
6.5
15.0
18.0
15.5
17.5
26.5
22.0
PLH
PHL
PLH
PHL
PLH
PHL
Propagation Delay
CWG to D/CW
Propagation Delay
5.5
6.0
10.5
8.5
S
to D/CW
n
7
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AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0°C to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
4.5
4.5
0
Max
Min
6.0
6.0
1.0
1.0
14.0
14.0
0
Max
Min
5.0
5.0
0
Max
t (H)
Setup Time, HIGH or LOW
S
t (L)
SEI to CP
S
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
SEI to CP
H
H
0
0
t (H)
Setup Time, HIGH or LOW
RFB to CP
11.0
11.0
0
12.5
12.5
0
S
t (L)
S
ns
ns
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
RFB to CP
H
H
0
0
0
t (H)
Setup Time, HIGH or LOW
13.5
13.0
0
16.0
15.5
0
15.0
14.5
0
S
t (L)
S to CP
1
S
t
t
(H)
(L)
Hold Time, HIGH or LOW
to CP
H
H
S
0
0
0
1
t (H)
Setup Time, HIGH or LOW
D to CP
9.0
9.0
0
11.5
11.5
0
10.0
10.0
0
S
t (L)
S
t
t
(H)
(L)
Hold Time, HIGH or LOW
D to CP
H
H
0
0
0
t (H)
Setup Time, HIGH or LOW
CWG to CP
7.0
5.5
0
9.0
8.0
0
8.0
6.5
0
S
t (L)
S
ns
ns
t
t
t
t
t
(H)
(L)
Hold Time, HIGH or LOW
CWG to CP
H
0
0
0
H
(H)
(L)
(H)
Clock Pulse Width
HIGH or LOW
4.0
4.0
4.0
7.0
5.0
7.0
4.5
4.5
4.5
W
W
W
MR Pulse Width, HIGH
ns
ns
t
t
(L)
P Pulse Width, LOW
Recovery Time
MR to CP
4.0
3.0
5.0
4.0
4.5
3.5
W
REC
REC
ns
t
Recovery Time
5.0
6.5
6.0
P to CP
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8
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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