74F403ASPC [FAIRCHILD]
First-In First-Out (FIFO) Buffer Memory; 先入先出（FIFO）缓冲存储器
| 型号： | 74F403ASPC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | First-In First-Out (FIFO) Buffer Memory |
| 文件： | 总15页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1989
Revised May 1999
74F403A
First-In First-Out (FIFO) Buffer Memory
General Description
Features
The 74F403A is an expandable fall-through type high-
speed First-In First-Out (FIFO) Buffer Memory optimized
for high-speed disk or tape controllers and communication
buffer applications. It is organized as 16-words by 4-bits
and may be expanded to any number of words or any num-
ber of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing eco-
nomical implementation of buffer memories.
■ Serial or parallel input
■ Serial or parallel output
■ Expandable without external logic
■ 3-STATE outputs
■ Fully compatible with all TTL families
■ Slim 24-pin package
■ 9403A replacement
The 74F403A has 3-STATE outputs which provide added
versatility and is fully compatible with all TTL families.
■ Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74F403ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
© 1999 Fairchild Semiconductor Corporation
DS009536.prf
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Unit Loading/Fan Out:
Block Diagram
See Section 2 for U.L. definitions
Input I /I
Pin
U.L.
HIGH/LOW
IH IL
Description
Output I /I
Names
OH OL
D
0 − D Parallel Data Inputs
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
3
D Serial Data Input
S
PL
Parallel Load Input
Serial Input Clock
Serial Input Enable
CPSI
IES
TTS
OES
TOS
TOP
MR
Transfer to Stack Input 1.0/0.667 20 µA/400 µA
Serial Output Enable
Transfer Out Serial
Transfer Out Parallel
Master Reset
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
1.0/0.667 20 µA/400 µA
OE
Output Enable
CPSO
Serial Output Clock
Q
Q
0 − Q Parallel Data Outputs
285/26.7
285/26.7
20/13.3
20/13.3
5.7 mA/16 mA
5.7 mA/16 mA
−400 µA/8 mA
−400 µA/8 mA
3
Serial Data Output
Input Register Full
Output Register Empty
S
IRF
ORE
Functional Description
As shown in the Block Diagram the 74F403A consists of
the F3 flip-flop and resetting the other flip-flops. The Q out-
three sections:
put of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
HIGH.
1. An Input register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
Parallel Entry— A HIGH on the PL input loads the D0-D3
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
Serial Entry— Data on the DS input is serially entered into
the F3, F2, F1, F0, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F0-F3. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 74F403A resulting from a 64-bit
serial bit train. B0 is the first bit, B63 the last bit.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
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2
FIGURE 1. Conceptual Input Section
Transfer to the Stack— The outputs of Flip-Flops F0-F3
feed the stack. A LOW level on the TTS input initiates a
“fall-through” action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
FIGURE 2. Final Positions in a 74F403A
Resulting from a 64-Bit Serial Train
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3-
STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
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FIGURE 3. Conceptual Output Section
Parallel Data Extraction— When the FIFO is empty after
transferred twice. If TOP goes HIGH and returns to LOW
before data is available from the stack, ORE remains LOW
indicating that there is no valid data at the outputs.
a LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided the “Trans-
fer Out Parallel” (TOP) input is HIGH. As a result of the
data transfer ORE goes HIGH, indicating valid data on the
data outputs (provided the 3-STATE buffer is enabled).
TOP can now be used to clock out the next word. When
TOP goes LOW, ORE will go LOW indicating that the out-
put data has been extracted, but the data itself remains on
the output bus until the next HIGH level at TOP permits the
transfer of the next word (if available) into the Output Reg-
ister. During parallel data extraction CPSO should be LOW.
TOS should be grounded for single slice operation or con-
nected to the appropriate ORE for expanded operation
(see Expansion section).
Serial Data Extraction— When the FIFO is empty after a
LOW pulse is applied to MR, the Output Register empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided TOS is
LOW and TOP is HIGH. As a result of the data transfer
ORE goes HIGH indicating valid data in the register. The 3-
STATE Serial Data Output, QS, is automatically enabled
and puts the first data bit on the output bus. Data is serially
shifted out on the HIGH-to-LOW transition of CPSO. To
prevent false shifting, CPSO should be LOW when the new
word is being loaded into the Output Register. The fourth
transition empties the shift register, forces ORE output
LOW and disables the serial output, QS (refer to Figure 3).
TOP is not edge triggered. Therefore, if TOP goes HIGH
before data is available from the stack, but data does
become available before TOP goes LOW again, that data
will be transferred into the Output Register. However, inter-
nal control circuitry prevents the same data from being
For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the
previous one has been shifted out.
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4
EXPANSION
Horizontal and Vertical Expansion— The 74F403A can
be expanded in both the horizontal and vertical directions
without any external parts and without sacrificing any of its
FIFO’s flexibility for serial/parallel input and output. The
interconnections necessary to form a 31-word by 16-bit
FIFO are shown in Figure 6. Using the same technique,
any FIFO of (15m + 1)-words by (4n)-bits can be con-
structed, where m is the number of devices in a column
and n is the number of devices in a row. Figure 7 and Fig-
ure 8 show the timing diagrams for serial data entry and
extraction for the 31-word by 16-bit FIFO shown in Figure
6. The final position of data after serial insertion of 496 bits
into the FIFO array of Figure 6 is shown in Figure 9.
Vertical Expansion— The 74F403A may be vertically
expanded to store more words without external parts. The
interconnection is necessary to form a 46-word by 4-bit
FIFO are shown in Figure 4. Using the same technique,
and FIFO of (15n + 1)-words by 4-bits can be constructed,
where n is the number of devices. Note that expansion
does not sacrifice any of the 74F403A’s flexibility for serial/
parallel input and output.
Interlocking Circuitry— Most conventional FIFO designs
provide status signals analogous to IRF and ORE. How-
ever, when these devices are operated in arrays, variations
in unit to unit operating speed require external gating to
assure all devices have completed an operation. The
74F403A incorporates simple but effective “master/slave”
interlocking circuitry to eliminate the need for external gat-
ing.
In the 74F403A array of Figure 6 devices 1 and 5 are
defined as “row masters” and the other devices are slaves
to the master in their row. No slave in a given row will initial-
ize its Input Register until it has received LOW on its IES
input from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go
HIGH until their OES inputs have gone HIGH.This inter-
locking scheme ensures that new input data may be
accepted by the array when the IRF output of the final
slave in that row goes HIGH and that output data for the
array may be extracted when the ORE of the final slave in
the output row goes HIGH.
The row master is established by connecting its IES input
to ground while a slave receives its IES input from the IRF
output of the next higher priority device. When an array of
74F403A FIFOs is initialized with a LOW on the MR inputs
of all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave
operation. Whenever MR and IES are LOW, the Master
Latch is set. Whenever TTS goes LOW the Request Initial-
ization Flip-Flop will be set. If the Master Latch is HIGH, the
Input Register will be immediately initialized and the
Request Initialization Flip-Flop reset. If the Master Latch is
reset, the Input Register is not initialized until IES goes
LOW. In array operation, activating the TTS initiates a rip-
ple input register initialization from the row master to the
last slave.
FIGURE 4. A Vertical Expansion Scheme
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE Request Flip-Flop. If the Master
Latch is set, the last Output Register Flip-Flop is set and
ORE goes HIGH. If the Master Latch is reset, the ORE out-
put will be LOW until an OES input is received.
5
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FIGURE 5. A Horizontal Expansion Scheme
FIGURE 6. A 31 x 16 FIFO Array
GRAPHIC 00953610
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6
FIGURE 7. Serial Data Entry for Array of Figure 6
FIGURE 8. Serial Data Extraction for Array of Figure 6
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FIGURE 9. Final Position of a 496-Bit Serial Input
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
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8
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +175°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
In HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
3-STATE Output
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
4000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min Type Max
Units
Conditions
CC
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
V
V
Input LOW Voltage
0.8
IL
Input Clamp Diode Voltage
−1.5
Min
Min
I
= −18 mA
CD
IN
V
Output HIGH
Voltage
10% V
10% V
2.5
2.5
I
I
= −400 µA (IRF, ORE)
OH
OL
CC
CC
OH
OH
= −5.7 mA (Q , Q )
n
s
V
5% V
5% V
2.7
2.7
0.5
I
I
= −400 µA (IRF, ORE)
CC
OH
OH
= −5.7 mA (Q , Q )
CC
n
s
V
Output LOW
Voltage
10% V
10% V
I
I
= 8 mA (IRF, ORE)
CC
CC
OL
OL
V
Min
0.5
20
= 16 mA (Q , Q )
n s
I
I
Input HIGH Current
µA
µA
Max
Max
V
= 2.7V
= 7.0V
= 0.5V
IH
IN
IN
IN
Input HIGH Current
BVI
100
V
Breakdown Test
I
I
I
I
I
I
Input LOW Current
−0.4
50
mA
µA
µA
mA
µA
mA
Max
Max
Max
Max
Max
Max
V
V
V
V
V
V
IL
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
= 2.7V
= 0.5V
= 0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
−50
−20
−130
250
= V
CEX
CCL
CC
170
= LOW
0
9
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AC Electrical Characteristics
T
= +25°C
T = 0° to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Figure
Number
Symbol
Parameter
Units
C
L
Min
Max
Min
Max
t
Propagation Delay,
Negative-Going
PHL
7.5
14.0
20.5
7.0
15.0
22.5
CPSI to IRF Output
Propagation Delay,
Negative-Going
Figure 11
Figure 12
ns
t
PLH
11.0
10.0
TTS to IRF
t
Propagation Delay,
Negative-Going
8.5
8.0
17.0
14.5
7.5
7.0
18.5
15.5
PLH
Figure 13
Figure 14
t
ns
ns
ns
PHL
CPSO to Q Output
S
t
Propagation Delay,
Positive-Going
10.0
8.5
18.0
15.5
9.0
8.0
20.0
16.5
PLH
t
Figure 15
PHL
TOP to Outputs Q -Q
0
3
t
Propagation Delay,
Negative-Going
PHL
Figure 13
Figure 14
9.5
8.0
17.5
15.0
22.0
22.0
13.0
17.0
18.0
15.5
9.0
7.5
19.0
16.5
25.0
25.0
14.0
19.5
20.5
17.5
CPSO to ORE
t
Propagation Delay,
Negative-Going
PHL
TOP to ORE
ns
ns
ns
Figure 15
t
Propagation Delay,
Positive-Going
PLH
12.5
12.5
7.0
11.5
11.0
6.5
TOP or ORE
t
Propagation Delay,
Negative-Going
PLH
Figure 13
Figure 14
TOS to Positive Going ORE
Propagation Delay,
Positive-Going
t
PHL
PL to Negative-Going IRF
Propagation Delay,
Negative-Going
Figure 17
Figure 18
t
PLH
9.5
8.5
PL to Positive-Going IRF
Propagation Delay,
Apostatize-Going
OES to ORE
t
PLH
10.0
8.5
9.0
ns
ns
t
Propagation Delay,
Positive-Going
PLH
7.5
Figure 18
IES to Positive-Going IRF
Propagation Delay,
MR to IRF
t
PLH
8.0
9.0
15.0
16.0
7.5
8.0
17.0
17.5
ns
ns
t
Propagation Delay,
MR to ORE
PHL
t
Propagation Delay,
OE to Q , Q , Q , Q
2.5
2.5
2.5
2.5
5.5
5.5
6.5
7.5
2.0
2.0
2.0
2.0
5.0
5.0
8.0
8.5
PZH
t
PZL
0
1
2
3
ns
ns
t
Propagation Delay,
OE to Q , Q , Q , Q
6.5
8.0
PHZ
t
7.5
8.0
PLZ
0
1
2
3
t
Propagation Delay,
Negative-Going
12.0
14.0
15.0
15.0
PZH
t
PZL
OES to Q
S
t
Propagation Delay,
Negative-Going
5.5
5.5
12.0
14.5
5.0
5.0
14.0
16.0
PHZ
t
PLZ
OES to Q
S
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10
AC Electrical Characteristics (Continued)
T
= +25°C
T = 0° to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Figure
Number
Symbol
Parameter
Units
C
L
Min
8.5
Max
Min
8.0
Max
t
t
t
t
Turn On Time
TOS to Q
21.0
20.0
80.0
24.0
21.0
95.0
PZH
ns
ns
8.5
8.0
PZL
DFT
AP
S
Fall Through Time
Parallel Appearance Time,
ORE to Q -Q
45.0
35.0
Figure 16
−10.0
−10.0
−1.0
−10.0
−10.0
−1.0
0
3
ns
t
Serial Appearance Time,
ORE to Q
AS
2.0
20
S
AC Operating Requirements
T
= +25°C
T = 0°C to +70°C
A
A
Figure
Number
Symbol
Parameter
V
= +5.0V
V
= +5.0V
Units
CC
CC
Min
1.0
1.0
Max
Min
1.0
1.0
Max
t (H)
S
Set-up Time HIGH or LOW
to Negative CPSI
t (L)
S
D
S
Figure 11
Figure 12
ns
t (H)
H
Hold Time, HIGH or LOW
to CPSI
3.5
3.5
3.5
3.5
t (L)
H
D
S
t (L)
Set-up Time, LOW
Figure 11
Figure 12
Figure 17
Figure 18
S
0
0
ns
ns
TTS to IRF
Serial or Parallel Mode
Set-up Time, LOW
t (L)
S
Figure 13
Figure 14
Negative-Going ORE to
0
0
Negative-Going TOS
Set-up Time, LOW
t (L)
S
3.0
4.0
ns
ns
Figure 12
Figure 12
Negative-Going IES to CPSI
Set-up Time, LOW
t (L)
S
14.0
15.5
Negative-Going TTS to CPSI
Set-up Time, HIGH or LOW
Parallel Inputs to PL
t (H)
0
0
S
t (L)
0
0
S
ns
t (H)
Hold Time, HIGH or LOW
Parallel Inputs to PL
2.0
2.0
2.5
2.5
H
t (L)
H
t
t
t
(H)
(L)
(H)
CPSI Pulse Width
HIGH or LOW
5.0
3.0
6.0
5.0
W
W
W
Figure 11
Figure 12
ns
ns
PL Pulse Width, HIGH
Figure 17
Figure 18
4.0
5.0
t
(L)
TTS Pulse Width, LOW
Serial or Parallel Mode
Figure 11
Figure 12
Figure 13
Figure 14
W
3.5
4.0
ns
ns
ns
Figure 16
t
t
t
(L)
(H)
(L)
MR Pulse Width, LOW
TOP Pulse Width
HIGH or LOW
3.5
4.5
3.5
4.0
5.5
4.0
W
W
W
Figure 15
t
t
t
(H)
(L)
CPSO Pulse Width
HIGH or LOW
4.5
3.0
5.5
4.0
Figure 13
Figure 14
W
ns
ns
W
Recovery Time
REC
5.0
5.5
Figure 16
MR to Any Input
11
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Timing Waveforms
Conditions: stack not full, IES, PL LOW
FIGURE 11. Serial Input, Unexpanded or Master Operation
Conditions: stack not full, IES HIGH when initiated, PL LOW
FIGURE 12. Serial Input, Expanded Slave Operation
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 13. Serial Output, Unexpanded or Master Operation
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Timing Waveforms (Continued)
Conditions: data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 14. Serial Output, Slave Operation
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 16. Fall Through Time
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Timing Waveforms (Continued)
Conditions: stack not full, IES LOW when initialized
NOTE A:TTS normally connected to IRF.
NOTE B: If stack is full, IRF will stay LOW.
FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
Conditions: stack not full, device initialized (Note 3) with IES HIGH
FIGURE 18. Parallel Load, Slave Mode
Note 3: Initialization requires a master reset to occur after power has been applied.
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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