74F413 [FAIRCHILD]
64 x 4 First-In First-Out Buffer Memory with Parallel I/O; 64 ×4的先入先出缓冲存储器，并行I / O
| 型号： | 74F413 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 64 x 4 First-In First-Out Buffer Memory with Parallel I/O |
| 文件： | 总5页 (文件大小：43K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I/O
General Description
Features
The F413 is an expandable fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits. The 4-bit input and output registers
record and transmit, respectively, asynchronous data in
parallel form. Control pins on the input and output allow for
handshaking and expansion. The 4-bit wide, 62-bit deep
fall-through stack has self-contained control logic.
■ Separate input and output clocks
■ Parallel input and output
■ Expandable without external logic
■ 15 MHz data rate
■ Supply current 160 mA max
■ Available in SOIC, (300 mil only)
Ordering Code:
Order Number Package Number
Package Description
74F413PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Data Inputs
Output IOH/IOL
HIGH/LOW
1.0/0.667
50/13.3
D0–D3
O0–O3
IR
20 µA/−0.4 mA
−1 mA/8 mA
Data Outputs
Input Ready
Shift In
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
20 µA/−0.4 mA
20 µA/−0.4 mA
20 µA/−0.4 mA
20 µA/−0.4 mA
20 µA/−0.4 mA
SI
SO
Shift Out
OR
Output Ready
Master Reset
MR
© 1999 Fairchild Semiconductor Corporation
DS009541
www.fairchildsemi.com
Functional Description
Data Input— Data is entered into the FIFO on D0–D3
defines the time required for the first data to travel from
input to the output of a previously empty device.
inputs. To enter data the Input Ready (IR) should be HIGH,
indicating that the first location is ready to accept data.
Data then present at the four data inputs is entered into the
first location when the Shift In (SI) is brought HIGH. An SI
HIGH signal causes the IR to go LOW. Data remains at the
first location until SI is brought LOW. When SI is brought
LOW and the FIFO is not full, IR will go HIGH, indicating
that more room is available. Simultaneously, data will prop-
agate to the second location and continue shifting until it
reaches the output stage or a full location. If the memory is
full, IR will remain LOW.
Data Output— Data is read from the O0–O3 outputs.
When data is shifted to the output stage, Output Ready
(OR) goes HIGH, indicating the presence of valid data.
When the OR is HIGH, data may be shifted out by bringing
the Shift Out (SO) HIGH. A HIGH signal at SO causes the
OR to go LOW. Valid data is maintained while the SO is
HIGH. When SO is brought LOW, the upstream data, pro-
vided that stage has valid data, is shifted to the output
stage. When new valid data is shifted to the output stage,
OR goes HIGH. If the FIFO is emptied, OR stays LOW, and
O0–O3 remains as before, i.e., data does not change if
Data Transfer— Once data is entered into the second cell,
the transfer of any full cell to the adjacent (downstream)
empty cell is automatic, activated by an on-chip control.
Thus data will stack up at the end of the device while empty
locations will “bubble” to the front. The tPT parameter
FIFO is empty.
Input Ready and Output Ready— may also be used as
status signals indicating that the FIFO is completely full
(Input Ready stays LOW for at least tPT) or completely
empty (Output Ready stays LOW for at least tPT).
Block Diagram
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.5
Min
Min
I
I
I
I
= −18 mA
CD
OH
IN
10% V
2.4
2.7
= −1 mA
= −1 mA
= 8 mA
= 2.7V
CC
OH
OH
OL
V
Voltage
5% V
CC
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
10% V
0.5
5.0
V
Min
OL
CC
I
I
µA
Max
V
V
V
IH
IN
BVI
7.0
50
µA
µA
V
Max
Max
0.0
= 7.0V
IN
I
Output HIGH Leakage Current
Input Leakage
= V
OUT CC
CEX
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
OD
3.75
µA
0.0
Circuit Current
All Other Pins Grounded
I
I
I
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−0.4
−130
160
mA
mA
mA
Max
Max
Max
V
V
V
= 0.5V
IL
IN
−20
= 0V
OS
CCH
OUT
115
= HIGH
O
3
www.fairchildsemi.com
AC Electrical Characteristics
T
= +25°C
T
= −55°C to +125°C
T = 0° to +70°C
A
A
A
V
= +5.0V
= 50 pF
Typ
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
10
Max
Min
8.0
8.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max
Min
10
Max
f
Shift In Rate
MHz
MHz
MAX
f
Shift Out Rate
10
10
MAX
t
Propagation Delay
Shift In to IR
1.5
1.5
1.5
1.5
1.5
1.5
1.5
44.0
31.0
52.0
31.0
46.0
34.0
27.0
50.0
37.0
57.0
37.0
52.0
39.0
33.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
48.0
35.0
55.0
35.0
50.0
37.0
31.0
PLH
ns
ns
t
PHL
t
Propagation Delay
Shift Out to OR
PLH
t
PHL
t
Propagation Delay
Output Data Delay
Propagation Delay
Master Reset to IR
Propagation Delay
Master Reset to OR
PLH
ns
ns
t
PHL
t
PLH
t
1.5
30.0
1.5
34.0
1.5
32.0
ns
PLH
AC Operating Requirements
T
= +25°C
T
= −55°C to +125°C
T = 0° to +70°C
A
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
1.0
Max
Min
1.0
Max
Min
1.0
Max
t (H)
Setup Time, HIGH or LOW
to SI
ns
S
t (L)
D
1.0
1.0
1.0
S
n
t
t
t
t
t
t
t
(H)
(L)
Hold Time, HIGH or LOW
to SI
10.0
10.0
5.0
10.0
10.0
5.0
10.0
10.0
5.0
H
D
H
n
(H)
(L)
(H)
(L)
(H)
Shift In Pulse Width
HIGH or LOW
ns
W
W
W
W
W
10.0
7.5
10.0
8.5
10.0
7.5
Shift Out Pulse Width
HIGH or LOW
10.0
7.5
10.0
8.5
10.0
7.5
Input Ready Pulse Width,
HIGH
ns
ns
ns
t
t
(L)
(L)
Output Ready Pulse Width,
LOW
5.0
5.0
5.0
W
W
Master Reset Pulse Width,
LOW
10.0
32.0
10.0
35.0
10.0
35.0
t
t
Recovery Time, MR to SI
Data Throughput Time
ns
REC
PT
0.9
1.0
1.0
µs
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5
www.fairchildsemi.com
相关型号：
©2020 ICPDF网 联系我们和版权申明