74F433SPCQR [FAIRCHILD]
Multi-Mode FIFO ; 多模式的FIFO
| 型号： | 74F433SPCQR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Multi-Mode FIFO
|
| 文件： | 总16页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F433
First-In First-Out (FIFO) Buffer Memory
General Description
Features
The 74F433 is an expandable fall-through type high-speed
First-In First-Out (FIFO) Buffer Memory that is optimized for
high-speed disk or tape controller and communication
buffer applications. It is organized as 64-words by 4-bits
and may be expanded to any number of words or any num-
ber of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing eco-
nomical implementation of buffer memories.
■ Serial or parallel input
■ Serial or parallel output
■ Expandable without additional logic
■ 3-STATE outputs
■ Fully compatible with all TTL families
■ Slim 24-pin package
■ 9423 replacement
The 74F433 has 3-STATE outputs that provide added ver-
satility, and is fully compatible with all TTL families.
Ordering Code:
Order Number Package Number
Package Description
74F433SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS009544
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
285/10
PL
Parallel Load Input
Serial Input Clock
Serial Input Enable
Transfer to Stack Input
Master Reset
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
5.7 mA/16 mA
5.7 µA/16 mA
400 µA/8 mA
400 µA/8 mA
CPSI
IES
TTS
MR
OES
TOP
TOS
CPSO
OE
Serial Output Enable
Transfer Out Parallel
Transfer Out Serial
Serial Output Clock
Output Enable
D0–D3
DS
Parallel Data Inputs
Serial Data Input
Q0–Q3
QS
Parallel Data Outputs
Serial Data Output
Input Register Full
Output Register Empty
285/10
IRF
20/5
ORE
20/5
Block Diagram
www.fairchildsemi.com
2
Functional Description
As shown in the block diagram, the 74F433 consists of
the last flip-flop (FC) is brought out as the Input Register
Full (IRF) signal. After initialization, this output is HIGH.
three sections:
1. An Input Register with parallel and serial data inputs,
as well as control inputs and outputs for input hand-
shaking and expansion.
Parallel Entry—A HIGH on the Parallel Load (PL) input
loads the D0–D3 inputs into the F0–F3 flip-flops and sets
the FC flip-flop. This forces the IRF output LOW, indicating
that the input register is full. During parallel entry, the Serial
Input Clock (CPSI) input must be LOW.
2. A 4-bit-wide, 62-word-deep fall-through stack with self-
contained control logic.
Serial Entry—Data on the Serial Data (DS) input is serially
3. An Output Register with parallel and serial data out-
puts, as well as control inputs and outputs for output
handshaking and expansion.
entered into the shift register (F3, F2, F1, F0, FC) on each
HIGH-to-LOW transition of the CPSI input when the Serial
Input Enable (IES) signal is LOW. During serial entry, the
PL input should be LOW.
These three sections operate asynchronously and are vir-
tually independent of one another.
Input Register (Data Entry)
After the fourth clock transition, the four data bits are
located in flip-flops F0–F3. The FC flip-flop is set, forcing
The Input Register can receive data in either bit-serial or 4-
bit parallel form. It stores this data until it is sent to the fall-
through stack, and also generates the necessary status
and control signals.
the IRF output LOW and internally inhibiting CPSI pulses
from affecting the register. Figure 2 illustrates the final posi-
tions in an 74F433 resulting from a 256-bit serial bit train
(B0 is the first bit, B255 the last).
This 5-bit register (see Figure 1) is initialized by setting flip-
flop F3 and resetting the other flip-flops. The Q-output of
FIGURE 1. Conceptual Input Section
3
www.fairchildsemi.com
fer, ORE goes HIGH, indicating valid data on the data out-
puts (provided that the 3-STATE buffer is enabled). The
TOP input can then be used to clock out the next word.
When TOP goes LOW, ORE also goes LOW, indicating
that the output data has been extracted; however, the data
itself remains on the output bus until a HIGH level on TOP
permits the transfer of the next word (if available) into the
output register. During parallel data extraction, the serial
output clock (CPSO) line should be LOW. The Transfer Out
Serial (TOS) line should be grounded for single-slice oper-
ation or connected to the appropriate ORE line for
expanded operation (refer to the “Expansion” section).
The TOP signal is not edge-triggered. Therefore, if TOP
goes HIGH before data is available from the stack but data
becomes available before TOP again goes LOW, that data
is transferred into the output register. However, internal
control circuitry prevents the same data from being trans-
ferred twice. If TOP goes HIGH and returns to LOW before
data is available from the stack, ORE remains LOW, indi-
cating that there is no valid data at the outputs.
FIGURE 2. Final Positions in an 74F433
Resulting from a 256-Bit Serial Train
Fall-Through Stack—The outputs of flip-flops F0–F3 feed
the stack. A LOW level on the Transfer to Stack (TTS) input
initiates a fall-through action; if the top location of the stack
is empty, data is loaded into the stack and the input register
is re-initialized. (Note that this initialization is delayed until
PL is LOW). Thus, automatic FIFO action is achieved by
connecting the IRF output to the TTS input.
Serial Extraction—When the FIFO is empty after a LOW
is applied to the MR input, the ORE output is LOW. After
data has been entered into the FIFO and has fallen through
to the bottom stack location, it is transferred into the output
register, if the TOS input is LOW and TOP is HIGH. As a
result of the data transfer, ORE goes HIGH, indicating that
valid data is in the register.
An RS-type flip-flop (the initialization flip-flop) in the control
section records the fact that data has been transferred to
the stack. This prevents multiple entry of the same word
into the stack even though IRF and TTS may still be LOW;
the initialization flip-flop is not cleared until PL goes LOW.
The 3-STATE Serial Data Output (QS) is automatically
enabled and puts the first data bit on the output bus. Data
is serially shifted out on the HIGH-to-LOW transition of
CPSO. To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the output register.
The fourth transition empties the shift register, forces ORE
LOW, and disables the serial output, QS. For serial opera-
Once in the stack, data falls through automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F433, the master reset (MR) input only initializes
the stack control section and does not clear the data.
Output Register
tion, the ORE output may be tied to the TOS input, request-
ing a new word from the stack as soon as the previous one
has been shifted out.
The Output Register (see Figure 3) receives 4-bit data
words from the bottom stack location, stores them, and out-
puts data on a 3-STATE, 4-bit parallel data bus or on a 3-
STATE serial data bus. The output section generates and
receives the necessary status and control signals.
Expansion
Vertical Expansion—The 74F433 may be vertically
expanded, without external components, to store more
words. The interconnections necessary to form a 190-word
by 4-bit FIFO are shown in Figure 4. Using the same tech-
nique, any FIFO of (63n+1)-words by 4-bits can be config-
Parallel Extraction—When the FIFO is empty after a LOW
pulse is applied to the MR input, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the output register, if the Transfer Out
Parallel (TOP) input is HIGH. As a result of the data trans-
ured, where
n is the number of devices. Note that
expansion does not sacrifice any of the 74F433 flexibility
for serial/parallel input and output.
www.fairchildsemi.com
4
FIGURE 3. Conceptual Output Section
5
www.fairchildsemi.com
FIGURE 4. A Vertical Expansion Scheme
Horizontal Expansion—The 74F433 can be horizontally
It should be noted that the horizontal expansion scheme
shown in Figure 5 exacts a penalty in speed.
expanded, without external logic, to store long words (in
multiples of 4-bits). The interconnections necessary to form
a 64-word by 12-bit FIFO are shown in Figure 5. Using the
same technique, any FIFO of 64-words by 4n-bits can be
constructed, where n is the number of devices.
Horizontal and Vertical Expansion—The 74F433 can be
expanded in both the horizontal and vertical directions
without any external components and without sacrificing
any of its FIFO flexibility for serial/parallel input and output.
The interconnections necessary to form a 127-word by 16-
bit FIFO are shown in Figure 6. Using the same technique,
any FIFO of (63m+1)-words by 4n-bits can be configured,
where m is the number of devices in a column and n is the
number of devices in a row. Figure 7 and Figure 8 illustrate
the timing diagrams for serial data entry and extraction for
the FIFO shown in Figure 6. Figure 9 illustrates the final
The right-most (most significant) device is connected to the
TTS inputs of all devices. Similarly, the ORE output of the
most significant device is connected to the TOS inputs of
all devices. As in the vertical expansion scheme, horizontal
expansion does not sacrifice any of the 74F433 flexibility
for serial/parallel input and output.
www.fairchildsemi.com
6
positions of bits in an expanded 74F433 FIFO resulting
from a 2032-bit serial bit train.
The row master is established by connecting its IES input
to ground, while a slave receives its IES input from the IRF
output of the next-higher priority device. When an array of
74F433 FIFOs is initialized with a HIGH on the MR inputs
of all devices, the IRF outputs of all devices are HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization.
Interlocking Circuitry—Most conventional FIFO designs
provide status signal analogous to IRF and ORE. However,
when these devices are operated in arrays, variations in
unit-to-unit operating speed require external gating to
ensure that all devices have completed an operation. The
74F433 incorporates simple but effective 'master/slave'
interlocking circuitry to eliminate the need for external gat-
ing.
Figure 10 is a conceptual logic diagram of the internal cir-
cuitry that determines master/slave operation. When MR
and IES are LOW, the master latch is set. When TTS goes
LOW, the initialization flip-flop is set. If the master latch is
HIGH, the input register is immediately initialized and the
initialization flip-flop reset. If the master latch is reset, the
input register is not initialized until IES goes LOW. In array
operation, activating TTS initiates a ripple input register ini-
tialization from the row master to the last slave.
In the 74F433 array of Figure 6, devices 1 and 5 are the
row masters; the other devices are slaves to the master in
their rows. No slave in a given row initializes its input regis-
ter until it has received a LOW on its IES input from a row
master or a slave of higher priority.
Similarly, the ORE outputs of slaves do not go HIGH until
their inputs have gone HIGH. This interlocking scheme
ensures that new input data may be accepted by the array
when the IRF output of the final slave in that row goes
HIGH and that output data for the array may be extracted
when the ORE output of the final slave in the output row
goes HIGH.
A similar operation takes place for the output register.
Either a TOS or TOP input initiates a load-from-stack oper-
ation and sets the ORE request flip-flop. If the master latch
is set, the last output register flip-flop is set and the ORE
line goes HIGH. If the master latch is reset, the ORE output
is LOW until
received.
a Serial Output Enable (OES) input is
FIGURE 5. A Horizontal Expansion Scheme
7
www.fairchildsemi.com
FIGURE 6. A 127 x 16 FIFO Array
FIGURE 7. Serial Data Entry for Array of Figure
www.fairchildsemi.com
8
FIGURE 8. Serial Data Extraction for Array of Figure
FIGURE 9. Final Position of a 2032-Bit Serial Input
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
9
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
−65°C to +150°C
−55°C to +125°C
−55°C to +150°C
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−30 mA to +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
IL
Input LOW Voltage
0.8
Input Clamp Diode Voltage
−1.5
Min
Min
I
= −18 mA
CD
IN
V
Output HIGH
Voltage
10% V
10% V
2.4
2.4
I
I
= 400 µA (ORE, IRF)
OH
OL
CC
OH
OH
= 5.7 mA (Q , Q )
CC
n
s
V
5% V
5% V
2.7
2.7
I
I
I
= 400 µA (ORE, IRF)
CC
OH
OH
OL
= 5.7 mA (Q , Q )
CC
n
s
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
10% V
0.50
5.0
V
Min
= 16 mA (Q , Q )
n s
CC
I
I
µA
Max
V
= 2.7V
= 7.0V
IH
IN
IN
V
BVI
7.0
50
µA
µA
V
Max
Max
0.0
I
Output HIGH
V
= V
CEX
OUT CC
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
OD
3.75
µA
0.0
Circuit Current
All Other Pins Grounded
I
I
I
I
I
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
−0.4
50
mA
µA
Max
Max
Max
Max
Max
V
V
V
V
= 0.5V
IL
IN
= 2.7V (Q , Q )
OZH
OZL
OS
CC
OUT
OUT
OUT
n
s
−50
−130
215
µA
= 0.5V (Q , Q )
n s
−20
mA
mA
= 0V
150
www.fairchildsemi.com
10
AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Figure
Number
Symbol
Parameter
Units
C
L
Min
Max
Min
Max
t
t
t
Propagation Delay, Negative-Going
CPSI to IRF Output
PHL
2.0
17.0
2.0
18.0
Figure 11
Figure 12
ns
Propagation Delay,
PLH
9.0
4.0
34.0
25.0
8.0
3.0
38.0
27.0
Negative-Going TTS to IRF
Propagation Delay, Negative-Going
PLH
Figure 13
Figure 14
ns
ns
ns
t
t
t
t
CPSO to Q Output
S
5.0
8.0
7.0
20.0
35.0
30.0
5.0
7.0
7.0
21.0
38.0
32.0
PHL
PLH
PHL
PHL
Propagation Delay, Positive-Going
Figure 15
TOP to Q –Q Outputs
0
3
Propagation Delay,
Figure 13
Figure 14
7.0
6.0
25.0
26.0
48.0
45.0
22.0
31.0
38.0
6.0
6.0
28.0
28.0
51.0
50.0
23.0
35.0
44.0
Negative-Going CPSO to ORE
Propagation Delay,
t
t
t
t
t
t
PHL
PLH
PLH
PHL
PLH
PLH
Negative-Going TOP to ORE
ns
ns
Figure 15
Propagation Delay, Positive-Going
13.0
13.0
4.0
12.0
12.0
4.0
TOP to ORE
Propagation Delay, Negative-Going
Figure 13
Figure 14
TOS to Positive-Going ORE
Propagation Delay, Positive-
Going PL to Negative-Going IRF
Propagation Delay, Negative-
Figure 17
Figure 18
ns
ns
7.0
6.0
Going PL to Positive-Going IRF
Propagation Delay,
9.0
8.0
Positive-Going OES to ORE
t
t
t
t
Propagation Delay Positive-IRF
PLH
PHL
PLH
PZH
5.0
7.0
25.0
28.0
5.0
7.0
27.0
31.0
ns
ns
ns
Figure 18
Going IES to Positive-Going
Propagation Delay
MR to ORE
Propagation Delay
5.0
1.0
27.0
16.0
5.0
1.0
30.0
18.0
MR to IRF
Enable Time
t
t
OE to Q –Q
3
1.0
1.0
14.0
10.0
1.0
1.0
16.0
12.0
PZL
PHZ
0
ns
ns
Disable Time
OE to Q –Q
3
t
t
1.0
1.0
23.0
10.0
1.0
1.0
30.0
12.0
PLZ
0
Enable Time
PZH
t
t
Negative-Going OES to Q
Disable Time
1.0
1.0
14.0
10.0
1.0
1.0
15.0
12.0
PZL
PHZ
S
t
t
Negative-Going OES to Q
Enable Time
1.0
1.0
14.0
35.0
1.0
1.0
16.0
42.0
PLZ
S
PZH
ns
ns
t
t
t
TOS to Q
1.0
0.2
35.0
0.9
1.0
0.2
39.0
1.0
PZL
DFT
AP
S
Fall-Through Time
Figure 16
Parallel Appearance Time
−20.0
−20.0
−2.0
−20.0
−20.0
−2.0
ORE to Q –Q
0
3
ns
t
Serial Appearance Time
ORE to Q
AS
5.0
5.0
S
11
www.fairchildsemi.com
AC Operating Requirements
T
= +25°C
= +5.0V
T = 0°C to +70°C
A
A
Figure
Number
Symbol
Parameter
V
Units
V
= +5.0V
CC
CC
Min
Max
Min
Max
t (H)
Setup Time, HIGH or LOW
to Negative CPSI
7.0
7.0
S
t (L)
D
7.0
2.0
7.0
2.0
S
S
Figure 11
Figure 12
ns
t
(H)
(L)
Hold Time, HIGH or LOW
to CPSI
H
t
D
2.0
2.0
H
S
t (L)
Setup Time, LOW TTS to IRF,
Serial or Parallel Mode
Figure 11
Figure 12
Figure 17
Figure 18
S
0.0
0.0
ns
ns
t (L)
Setup Time, LOW Negative-Going
S
Figure 13
Figure 14
0.0
8.0
0.0
9.0
ORE to Negative-Going TOS
t (L)
Setup Time, LOW Negative-Going
S
IES to CPSI
ns
ns
Figure 12
t (L)
Setup Time, LOW Negative-Going
S
30.0
33.0
TTS to CPSI
t (H)
Setup Time, HIGH or LOW
Parallel Inputs to PL
Hold Time, HIGH or LOW
Parallel Inputs to PL
0.0
0.0
4.0
4.0
0.0
0.0
4.0
4.0
S
t (L)
S
t
(H)
(L)
H
t
H
t
(H)
(L)
(H)
CPSI Pulse Width
HIGH or LOW
10.0
5.0
11.0
6.0
W
Figure 11
Figure 12
ns
ns
t
W
t
PL Pulse Width, HIGH
7.0
9.0
Figure 17
Figure 18
W
t
(L)
W
TTS Pulse Width, LOW
Serial or Parallel Mode
Figure 11
Figure 12
Figure 13
Figure 14
7.0
9.0
ns
t
(L)
(H)
(L)
MR Pulse Width, LOW
TOP Pulse Width
HIGH or LOW
7.0
14.0
7.0
9.0
16.0
7.0
ns
ns
Figure 16
Figure 15
W
t
W
t
W
t
(H)
(L)
CPSO Pulse Width
HIGH or LOW
14.0
7.0
16.0
7.0
Figure 13
Figure 14
W
ns
ns
t
W
t
Recovery Time
REC
8.0
15.0
Figure 16
MR to Any Input
www.fairchildsemi.com
12
Timing Waveforms
Conditions: Stack not full, IES, PL LOW
FIGURE 11. Serial Input, Unexpanded or Master Operation
Conditions: Stack not full, IES HIGH when initiated, PL LOW
FIGURE 12. Serial Input, Expanded Slave Operation
Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 13. Serial Output, Unexpanded or Master Operation
13
www.fairchildsemi.com
Timing Waveforms (Continued)
Conditions: Data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 14. Serial Output, Slave Operation
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 16. Fall Through Time
www.fairchildsemi.com
14
Timing Waveforms (Continued)
Conditions: Stack not full, IES LOW when initialized
NOTE A: TTS normally connected to IRF.
NOTE B: If stack is full, IRF will stay LOW.
FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
Conditions: Stack not full, device initialized (Note 3) with IES HIGH
Note 3: Initialization requires a master reset to occur after power has been applied.
FIGURE 18. Parallel Load, Slave Mode
15
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
16
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明