74F676 [FAIRCHILD]
16-Bit Serial/Parallel-In, Serial-Out Shift Register; 16位串行/并行-IN ，串行输出移位寄存器
| 型号： | 74F676 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Serial/Parallel-In, Serial-Out Shift Register |
| 文件： | 总6页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F676
16-Bit Serial/Parallel-In, Serial-Out Shift Register
General Description
Features
■ 16-bit parallel-to-serial conversion
■ 16-bit serial-in, serial-out
■ Chip select control
The 74F676 contains 16 flip-flops with provision for syn-
chronous parallel or serial entry and serial output. When
the Mode (M) input is HIGH, information present on the
parallel data (P0–P15) inputs is entered on the falling edge
■ Slim 24 lead 300 mil package
of the Clock Pulse (CP) input signal. When M is LOW, data
is shifted out of the most significant bit position while infor-
mation present on the Serial (SI) input shifts into the least
significant bit position. A HIGH signal on the Chip Select
(CS) input prevents both parallel and serial operations.
Ordering Code:
Order Number Package Number
Package Description
74F676SC
74F676PC
74F676SPC
M24B
N24A
N24C
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009588
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Output IOH/IOL
HIGH/LOW
1.0/1.0
P0–P15
CS
Parallel Data Inputs
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
Chip Select Input (Active LOW)
Clock Pulse Input (Active LOW)
1.0/1.0
1.0/1.0
CP
M
Mode Select Input
Serial Data Input
Serial Output
1.0/1.0
1.0/1.0
50/33.3
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
SI
SO
Functional Description
Shift Register Operations Table
The 16-bit shift register operates in one of three modes, as
indicated in the Shift Register Operations Table.
Control Input
Operating Mode
HOLD— a HIGH signal on the Chip Select (CS) input pre-
vents clocking, and data is stored in the sixteen registers.
CS
H
M
X
L
CP
X
Hold
Shift/Serial Load— data present on the SI pin shifts into
the register on the falling edge of CP. Data enters the Q0
L
Shift/Serial Load
Parallel Load
position and shifts toward Q15 on successive clocks, finally
appearing on the SO pin.
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Parallel Load— data present on P0–P15 are entered into
the register on the falling edge of CP. The SO output repre-
sents the Q15 register output.
= HIGH-to-LOW Transition
To prevent false clocking, CP must be LOW during a LOW-
to-HIGH transition of CS.
Block Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
= −18 mA
CD
OH
IN
10% V
2.5
2.7
= −1 mA
= −1 mA
CC
OH
OH
V
V
Voltage
5% V
CC
V
Output LOW
OL
10% V
0.5
5.0
7.0
50
Min
Max
Max
Max
0.0
I
= 20 mA
= 2.7V
= 7.0V
CC
OL
Voltage
I
Input HIGH
IH
µA
µA
µA
V
V
V
V
IN
Current
I
Input HIGH Current
Breakdown Test
Output HIGH
BVI
IN
I
CEX
= V
OUT
CC
Leakage Current
Input Leakage
Test
V
I
= 1.9 µA,
ID
ID
4.75
All Other Pins Grounded
V = 150 mV,
IOD
I
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
OD
3.75
µA
0.0
All Other Pins Grounded
I
−0.6
−150
72
mA
mA
mA
Max
Max
Max
V
V
= 0.5V
IL
IN
I
−60
= 0V
OUT
OS
I
CC
3
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AC Electrical Characteristics
T
= +25°C
T
= −55°C to 125°C
T = 0°C to +70°C
A
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
CC
Symbol
Parameter
Units
C
C
L
L
Min
100
4.5
Typ
110
9.0
Max
Min
45
Max
Min
90
Max
f
t
t
Maximum Clock Frequency
Propagation Delay
MHz
ns
MAX
11.0
12.5
4.5
5.0
17.0
14.5
4.5
5.0
12.0
13.5
PLH
PHL
5.0
9.0
CP to SO
AC Operating Requirements
T
= +25°C
T
= −55°C to 125°C
T , V = ____
A CC
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
V = +5.0V
CC
Units
CC
CC
Min
4.0
4.0
Max
Min
4.0
4.0
Max
Min
4.0
4.0
Max
t (H)
S
Setup Time, HIGH or LOW
t (L)
S
SI to CP
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
4.0
4.0
3.0
3.0
4.0
4.0
8.0
8.0
2.0
2.0
H
SI to CP
H
t (H)
S
Setup Time, HIGH or LOW
t (L)
S
P
to CP
n
ns
ns
t
t
(H)
(L)
Hold Time, HIGH or LOW
to CP
H
P
H
n
t (H)
S
Setup Time, HIGH or LOW
t (L)
S
M to CP
t
t
(H)
(L)
Hold Time, HIGH or LOW
H
M to CP
H
t (L)
Setup Time, LOW
S
10.0
10.0
12.0
10.0
10.0
10.0
CS to CP
ns
ns
t
(H)
Hold Time, HIGH
CS to CP
H
t
t
(H)
(L)
4.0
6.0
5.0
9.0
4.0
6.0
W
CP Pulse Width
HIGH or LOW
W
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4
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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www.fairchildsemi.com
6
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