74F845 [FAIRCHILD]
8-Bit Transparent Latch; 8位透明锁存器
| 型号： | 74F845 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Transparent Latch |
| 文件： | 总6页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1988
Revised August 1999
74F845
8-Bit Transparent Latch
General Description
Features
The 74F845 bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and pro-
vide extra data width for wider address/data paths or buses
carrying parity.
■ 3-STATE outputs
■ Direct replacement for AMD’s Am29845
The 74F845 is functionally- and pin-compatible with AMD’s
Am29845.
Ordering Code:
Order Number Package Number
Package Description
74F845SC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F845SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009601
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Data Inputs
Output IOH/IOL
HIGH/LOW
1.0/1.0
D0–D7
20 µA/−0.6 mA
−3.0 µA/24 mA
20 µA/−0.6 mA
O0–O7
Data Outputs
150/40
Output Enables
1.0/1.0
OE1–OE3
LE
Latch Enable
Clear
1.0/1.0
1.0/1.0
1.0/1.0
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
CLR
PRE
Preset
Functional Description
Function Table
The 74F845 consists of eight D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
Inputs
Internal Output
Function
CLR PRE OE LE
D
X
L
Q
X
O
Z
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
L
X
H
H
L
High Z
L
Z
High Z
H
X
L
H
Z
High Z
NC
L
Z
Latched
Transparent
Transparent
Latched
Preset
H
H
L
L
L
H
X
X
X
X
X
X
H
H
NC
H
L
L
NC
H
L
X
X
X
L
H
L
L
L
Clear
L
L
H
H
Z
Preset
L
H
L
H
H
L
Latched
Latched
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
I
I
I
= −18 mA
CD
OH
IN
10% V
10% V
5% V
2.5
2.4
2.7
2.7
= −1 mA
= −3 mA
= −1 mA
= −3 mA
= 24 mA
= 2.7V
CC
CC
CC
CC
CC
OH
OH
OH
OH
OL
Voltage
V
5% V
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
10% V
0.5
5.0
V
Min
OL
I
µA
Max
V
IH
IN
I
BVI
7.0
50
µA
µA
V
Max
Max
0.0
V
= 7.0V
IN
I
Output HIGH
CEX
V
= V
CC
OUT
Leakage Current
Input Leakage
V
I
= 1.9 µA
ID
ID
4.75
Test
All Other Pins Grounded
V = 150 mV
IOD
I
Output Leakage
OD
3.75
µA
0.0
Circuit Current
All Other Pins Grounded
I
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
−0.6
50
mA
µA
µA
mA
µA
mA
Max
Max
Max
Max
0.0V
Max
V
V
V
V
V
V
= 0.5V
IL
IN
I
= 2.7V
= 0.5V
= 0V
OZH
OUT
OUT
OUT
OUT
I
−50
−150
500
85
OZL
I
−60
OS
I
= 5.25V
ZZ
I
63
= HIGH Z
O
CCZ
3
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AC Electrical Characteristics
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
2.5
1.5
5.0
2.0
Typ
4.8
3.6
8.1
4.4
Max
8.0
Min
2.0
1.5
4.5
2.0
Max
t
Propagation Delay
to O
9.0
7.0
PLH
ns
ns
ns
t
D
6.5
PHL
n
n
t
Propagation Delay
LE to O
12.0
7.5
13.5
8.0
PLH
t
PHL
n
t
Propagation Delay
PRE to O
PLH
3.0
3.0
5.9
6.5
10.0
10.0
2.5
2.5
11.0
11.0
n
t
Propagation Delay
CLR to O
PHL
ns
ns
ns
n
t
Output Enable Time
2.5
2.5
5.8
7.6
9.5
2.0
2.0
10.5
13.0
PZH
t
12.0
OE to O
n
PZL
t
Output Disable Time
1.0
1.0
3.1
2.8
7.5
6.5
1.0
1.0
8.5
7.5
PHZ
t
OE to O
n
PLZ
AC Operating Requirements
T
= +25°C
T = 0°C to +70°C
A
A
Symbol
Parameter
V
= +5.0V
V
= +5.0V
CC
Units
CC
Min
2.0
2.0
2.5
3.0
4.0
Max
Min
2.5
2.5
3.0
3.5
4.0
Max
t (H)
Setup Time, HIGH or LOW
to LE
S
ns
ns
t (L)
D
n
S
t (H)
Hold Time, HIGH or LOW
to LE
H
t (L)
D
n
H
t
t
t
(H)
(L)
(L)
LE Pulse Width, HIGH
PRE Pulse Width, LOW
ns
ns
ns
W
W
W
5.0
5.0
5.0
5.0
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
t
t
10.0
12.0
10.0
13.0
ns
ns
REC
REC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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