74FR74SC [FAIRCHILD]
Dual D-Type Flip-Flop; 双D型触发器
| 型号： | 74FR74SC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Flip-Flop |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1992
Revised August 1999
74FR74 • 74FR1074
Dual D-Type Flip-Flop
General Description
Features
The 74FR74 and 74FR1074 are dual D-type flip-flops with
true and complement (Q/Q) outputs. On the 74FR74, data
at the D inputs is transferred to the outputs on the rising
edge of the clock input (CPn). The 74FR1074 is the nega-
■ 74FR74 is pin-for-pin compatible with the 74F74
■ True 150 MHz fMAX capability on 74FR74
■ Outputs sink 24 mA and source 24 mA
■ Guaranteed pin-to-pin skew specifications
tive edge triggered version of this device. Both parts fea-
ture asynchronous clear (CDn) and set (SDn) inputs which
are low level enabled.
Ordering Code:
Order Number Package Number
Package Description
74FR74SC
M14A
N14A
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74FR74PC
74FR1074SC
74FR1074PC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74FR74
74FR1074
© 1999 Fairchild Semiconductor Corporation
DS010977
www.fairchildsemi.com
Logic Symbols
Pin Descriptions
Pin Names
Description
74FR74
Dn
Data Inputs
Clock Inputs
CPn
SDn
CDn
Qn
Asynchronous Set Inputs
Asynchronous Clear Inputs
True Output
Complementary Output
Qn
Truth Tables
74FR74
Inputs
CD
Outputs
SD
L
CP
X
D
X
X
X
H
L
Q
Q
L
H
L
H
L
H
L
X
H
H
L
L
X
H
H
H
H
H
H
H
H
L
H
L
X
Q0
Q0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
74FR1074
= Rising Edge
Q
= Previous Q(Q) before LOW-to-HIGH Clock Transition
0
74FR1074
Inputs
CD
Outputs
SD
L
CP
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
L
X
H
H
L
L
X
H
H
L
H
H
H
H
H
H
H
L
X
Q0
Q0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
= Falling Edge
Q
= Previous Q(Q) before HIGH-to-LOW Clock Transition
0
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2
Logic Diagrams
74FR74
74FR1074
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
2000V
ESD Last Passing Voltage (Min)
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
CC
V
V
V
V
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
IH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
V
Min
Min
Min
Min
Min
Max
I
I
I
I
I
= −18 mA
CD
OH
IN
2.5
2.4
2.0
V
= −1 mA
= −3 mA
= −24 mA
= 24 mA
= 2.7V
OH
OH
OH
OL
Voltage
V
V
V
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
0.5
5
V
OL
I
µA
V
IH
IN
I
BVI
7
µA
Max
V
= 7.0V
IN
I
Input LOW Current
−150
−1.8
µA
mA
V
Max
Max
0.0
V
V
= 0.5V (D , CP )
IL
IN
n
n
= 0.5V (C , S
)
IN
Dn
Dn
V
Input Leakage Test
4.75
I
= 1.9 µA,
ID
ID
All Other Pins Grounded
V = 150 mV,
IOD
I
Output Circuit
3.75
V
0.0
OD
Leakage Test
All Other Pins Grounded
I
Output Short-Circuit Current
Output HIGH
−100
−275
mA
Max
Max
V
V
= 0.0V
OS
OUT
OUT
I
50
µA
= V
CC
CEX
Leakage Current
Power Supply Current
I
24
mA
Max
CC
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4
AC Electrical Characteristics 74FR74
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
150
2.5
Typ
190
3.5
Max
Min
150
2.5
Max
f
t
t
Maximum Clock Frequency
MHz
ns
MAX
Propagation Delay
CP to Q or Q
5.0
6.0
5.0
6.0
PLH
PHL
2.5
4.5
2.5
n
n
n
t
t
Propagation Delay
or S to Q or Q
n
1.5
2.0
3.5
5.5
5.5
7.0
1.5
2.0
5.5
7.0
PLH
PHL
ns
ns
ns
ns
C
Dn
Dn
n
t
Pin to Pin Skew
OSHL
1.0
1.0
3.0
(Note 3)
for HL Transitions
Pin to Pin Skew
t
OSLH
(Note 3)
for LH Transitions
Pin to Pin Skew
t
OST
(Note 3)
for HL/LH Transitions
t
True/Complement
Output Skew
Q/Q
1.8
1.8
ns
ns
(Note 3)
t
Pin (Signal)
PS
(Note 3)
Transition Variation
Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t ) or LOW-to-HIGH (t ) or in opposite directions
OSHL
OSLH
both HL and LH (t
). t
is guaranteed by design.
OST OST
AC Operating Requirements 74FR74
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
2.5
2.5
0
Max
Min
2.5
2.5
0
Max
t (H)
Setup Time, HIGH or LOW
to CP
S
ns
ns
ns
t (L)
D
n
S
n
t (H)
Hold Time, HIGH or LOW
to CP
H
t (L)
D
0
0
H
n
n
t
t
(H)
(L)
CP Pulse Width
n
3.3
3.3
3.3
3.3
W
W
HIGH or LOW
(Note 4)
t
t
(L)
4.0
2.0
4.0
2.0
ns
ns
W
S
or C Pulse Width
Dn Dn
Recovery Time
or C to CP
n
REC
S
Dn
Dn
Note 4: This specification is guaranteed by design.
5
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AC Electrical Characteristics 74FR1074
T
= +25°C
T = 0°C to +70°C
A
A
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
CC
CC
Symbol
Parameter
Units
C
L
Min
120
2.5
Typ
160
4.0
Max
Min
120
2.5
Max
f
Maximum Clock Frequency
MHz
ns
MAX
t
Propagation Delay
CP to Q or Q
5.5
6.5
5.5
6.5
PLH
t
3.0
5.0
3.0
PHL
n
n
n
t
Propagation Delay
or S to Q or Q
n
1.5
2.0
3.5
5.5
5.5
7.0
1.5
2.0
5.5
7.0
PLH
ns
ns
ns
ns
t
C
PHL
Dn
Dn
n
t
Pin to Pin Skew
OSHL
1.5
1.5
3.5
(Note 5)
for HL Transitions
Pin to Pin Skew
t
OSLH
(Note 5)
for LH Transitions
Pin to Pin Skew
t
OST
(Note 5)
for HL/LH Transitions
t
True/Complement
Output Skew
Q/Q
2.0
2.0
ns
ns
(Note 5)
t
Pin (Signal)
PS
(Note 5)
Transition Variation
Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t ) or LOW-to-HIGH (t ) or in opposite directions
OSHL
OSLH
both HL and LH (t
). t
is guaranteed by design.
OST OST
AC Operating Requirements 74FR1074
T
= +25°C
T = 0°C = +70°C
A
A
Symbol
Parameter
V
= +5.0V
= 50 pF
V
= +5.0V
C = 50 pF
L
Units
CC
CC
C
L
Min
2.0
2.0
0
Max
Min
2.0
2.0
0
Max
t (H)
Setup Time, HIGH or LOW
to CP
S
ns
ns
t (L)
D
n
S
n
t (H)
Hold Time, HIGH or LOW
to CP
H
t (L)
D
0
0
H
n
n
t
t
(H)
(L)
3.3
3.3
3.3
3.3
CP Pulse Width
n
W
ns
HIGH or LOW
W
(Note 6)
t
t
(L)
4.0
2.0
4.0
2.0
ns
ns
W
S
or C Pulse Width
Dn Dn
Recovery Time
or C to CP
n
REC
S
Dn
Dn
Note 6: This specification is guaranteed by design.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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TI
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