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74LCX573MTCX-NL3 [FAIRCHILD]

Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs; 低电压八路锁存器与5V容限输入和输出
74LCX573MTCX-NL3
型号： 74LCX573MTCX-NL3
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs
低电压八路锁存器与5V容限输入和输出

锁存器
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中文：  中文翻译
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February 2006  
74LCX573  
Low Voltage Octal Latch with 5V Tolerant  
Inputs and Outputs  
Features  
General Description  
■ 5V tolerant inputs and outputs  
The LCX573 is a high-speed octal latch with buffered  
common Latch Enable (LE) and buffered common Out-  
put Enable (OE) input.  
■ 2.3V–3.6V V specifications provided  
CC  
■ 7.0 ns t max (V = 3.3V), 10µA I max  
PD  
CC  
CC  
The LCX573 is functionally identical to the LCX373 but  
has inputs and outputs on opposite sides.  
■ Power down high impedance inputs and outputs  
1
■ Supports live insertion/withdrawal  
■ ±24mA output drive (V = 3.0V)  
The LCX573 is designed for low voltage applications with  
capability of interfacing to a 5V signal environment. The  
LCX573 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintain-  
ing CMOS low power dissipation.  
CC  
■ Implements patented noise/EMI reduction circuitry  
■ Latch-up performance exceeds JEDEC 78 conditions  
■ ESD performance  
– Human body model > 2000V  
– Machine model > 200V  
■ Leadless Pb-Free DQFN package  
Ordering Information  
Package  
Order Number  
Number  
Package Description  
74LCX573WM  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"  
Wide  
74LCX573SJ  
M20D  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
2
74LCX573BQX  
MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads  
(DQFN), JEDEC MO-241, 2.5 x 4.5mm  
74LCX573MSA  
MSA20  
MTC20  
MTC20  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm  
Wide  
74LCX573MTC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,  
4.4mm Wide  
3
74LCX573MTCX_NL  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC  
MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Notes  
1. To ensure the high impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the driver.  
2. DQFN package available in Tape and Reel only.  
3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
©2006 Fairchild Semiconductor Corporation  
74LCX573 Rev. 2.0.0  
1
www.fairchildsemi.com  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
D0 D1 D2 D3 D4 D5 D6 D7  
LE  
D –D  
Data Inputs  
0
7
LE  
Latch Enable Input  
OE  
O0 O1 O2 O3 O4 O5 O6 O7  
OE  
3-STATE Output Enable Input  
3-STATE Latch Outputs  
O –O  
0
7
Connection Diagrams  
Truth Table  
Pin Assignments for  
SOIC, SOP, SSOP, TSSOP  
Inputs  
LE  
Outputs  
OE  
L
D
H
L
O
n
OE  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
H
H
L
H
D0  
D1  
L
L
D2  
D3  
D4  
D5  
L
X
X
O
0
H
X
Z
H = HIGH Voltage  
L = LOW Voltage  
Z = High Impedance  
X = Immaterial  
D6  
D7  
GND  
LE  
O = Previous O before HIGH-to-LOW transition of Latch  
0
0
Pad Assignments for DQFN  
Enable  
VCC  
20  
OE  
1
Functional Description  
19  
18  
17  
16  
15  
14  
13  
12  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
2
3
4
5
6
7
8
9
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
The LCX573 contains eight D-type latches with 3-STATE  
output buffers. When the Latch Enable (LE) input is  
HIGH, data on the D inputs enters the latches. In this  
n
condition the latches are transparent, i.e., a latch output  
will change state each time its D input changes. When  
LE is LOW the latches store the information that was  
present on the D inputs a setup time preceding the  
HIGH-to-LOW transition of LE. The 3-STATE buffers are  
controlled by the Output Enable (OE) input. When OE is  
LOW, the buffers are enabled. When OE is HIGH the  
buffers are in the high impedance mode but this does not  
interfere with entering new data into the latches.  
10  
11  
GND LE  
(Top View)  
Logic Diagram  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
OE  
O
O
O
O
O
O
O
O
7
0
1
2
3
4
5
6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate  
propagation delays.  
2
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Absolute Maximum Ratings  
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The  
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are  
not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the  
conditions for actual device operation.  
Symbol  
Parameter  
Conditions  
Value  
Units  
V
V
Supply Voltage  
−0.5 to +7.0  
−0.5 to +7.0  
−0.5 to +7.0  
V
V
V
CC  
I
DC Input Voltage  
V
DC Output Voltage  
Output in 3-STATE  
Output in HIGH or LOW State  
V < GND  
O
4
−0.5 to V + 0.5  
CC  
I
I
DC Input Diode Current  
DC Output Diode Current  
−50  
−50  
mA  
mA  
IK  
I
V
< GND  
OK  
O
V
> V  
+50  
O
CC  
I
I
I
DC Output Source/Sink Current  
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature  
±50  
mA  
mA  
mA  
°C  
O
±100  
CC  
GND  
±100  
T
−65 to +150  
STG  
5
Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min.  
2.0  
1.5  
0
Max.  
3.6  
Units  
V
Supply Voltage  
Operating  
V
CC  
Data Retention  
3.6  
V
Input Voltage  
5.5  
V
V
I
V
Output Voltage  
HIGH or LOW State  
3-STATE  
0
V
CC  
O
0
5.5  
±24  
±12  
±8  
I
/I  
Output Current  
V
V
V
= 3.0V − 3.6V  
= 2.7V − 3.0V  
= 2.3V − 2.7V  
mA  
OH OL  
CC  
CC  
CC  
T
Free-Air Operating Temperature  
Input Edge Rate  
−40  
85  
°C  
A
∆t/∆V  
V
= 0.8V − 2.0V, V = 3.0V  
0
10  
ns/V  
IN  
CC  
Notes:  
4.  
I Absolute Maximum Rating must be observed.  
O
5. Unused (inputs or I/Os) must be held HIGH or LOW. They may not float.  
3
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
DC Electrical Characteristics  
T = −40°C to +85°C  
A
Symbol  
Parameter  
Conditions  
V
(V)  
Min.  
1.7  
Max.  
Units  
CC  
V
V
V
HIGH Level Input Voltage  
2.3 − 2.7  
2.7 − 3.6  
2.3 − 2.7  
2.7 − 3.6  
2.3 − 3.6  
2.3  
V
IH  
2.0  
LOW Level Input Voltage  
0.7  
0.8  
V
V
IL  
HIGH Level Output  
Voltage  
I
I
I
I
I
I
I
I
I
I
= −100µA  
V
− 0.2  
OH  
OH  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
CC  
= −8mA  
= −12mA  
= −18mA  
= −24mA  
= 100µA  
= 8mA  
1.8  
2.2  
2.4  
2.2  
2.7  
3.0  
3.0  
V
LOW Level Output  
Voltage  
2.3 − 3.6  
2.3  
0.2  
0.6  
V
OL  
= 12mA  
= 16mA  
= 24mA  
2.7  
0.4  
3.0  
0.4  
3.0  
0.55  
±5.0  
±5.0  
I
I
Input Leakage Current  
0 ≤ V ≤ 5.5V  
2.3 − 3.6  
2.3 − 3.6  
µA  
µA  
I
I
3-STATE Output Leakage  
0 ≤ V ≤ 5.5V, V = V or  
O I IH  
OZ  
V
IL  
I
I
Power-Off Leakage Current V or V = 5.5V  
0
10  
10  
µA  
µA  
OFF  
I
O
Quiescent Supply Current  
V = V or GND  
2.3 − 3.6  
2.3 − 3.6  
2.3 − 3.6  
CC  
I
CC  
6
3.6V ≤ V , V ≤ 5.5V  
±10  
500  
I
O
∆I  
Increase in I per Input  
V
= V −0.6V  
µA  
CC  
CC  
IH  
CC  
AC Electrical Characteristics  
T = −40°C to +85°C, R = 500 Ω  
A
L
V
= 3.3V ± 0.3V  
V
= 2.7V  
V = 2.5 ± 0.2V  
CC  
CC  
CC  
C = 50pF  
C = 50pF  
C = 30pF  
L
L
L
Symbol  
Parameter  
Min.  
Max.  
8.0  
Min.  
1.5  
1.5  
1.5  
1.5  
2.5  
1.5  
3.3  
Max.  
9.0  
Min.  
Max. Units  
t
t
t
t
t
t
t
, t  
Propagation Delay, D to O  
n
1.5  
1.5  
1.5  
1.5  
2.5  
1.5  
3.3  
1.5  
1.5  
1.5  
1.5  
4.0  
2.0  
4.0  
9.6  
10.5  
10.5  
7.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PHL PLH  
n
, t  
Propagation Delay, LE to O  
Output Enable Time  
8.5  
9.5  
PHL PLH  
n
, t  
8.5  
9.5  
PZL PZH  
, t  
Output Disable Time  
6.5  
7.0  
PLZ PHZ  
Setup Time, D to LE  
S
n
Hold Time, D to LE  
H
W
n
LE Pulse Width  
7
t
t
,
Output to Output Skew  
1.0  
OSHL  
OSLH  
Notes:  
6. Outputs disabled or 3-STATE only.  
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the  
same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-  
OSHL  
HIGH (t  
).  
OSLH  
4
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Dynamic Switching Characteristics  
T = 25°C  
A
Symbol  
Parameter  
Conditions  
V
(V)  
Typical  
0.8  
Units  
CC  
V
Quiet Output Dynamic Peak V  
C = 50pF, V = 3.3V, V = 0V  
3.3  
V
OLP  
OL  
L
IH  
IL  
C = 30pF, V = 2.5V, V = 0V  
2.5  
3.3  
2.5  
0.6  
L
IH  
IL  
V
Quiet Output Dynamic Valley V  
C = 50pF, V = 3.3V, V = 0V  
−0.8  
−0.6  
V
OLV  
OL  
L
IH  
IL  
C = 30pF, V = 2.5V, V = 0V  
L
IH  
IL  
Capacitance  
Symbol  
Parameter  
Conditions  
Typical  
Units  
C
C
C
Input Capacitance  
Output Capacitance  
Power Dissipation Capacitance  
V
V
V
= Open, V = 0V or V  
CC  
7
8
pF  
pF  
pF  
IN  
CC  
CC  
CC  
I
= 3.3V, V = 0V or V  
CC  
OUT  
PD  
I
= 3.3V, V = 0V or V , f = 10 MHz  
25  
I
CC  
5
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
AC Loading and Waveforms (Generic for LCX Family)  
V
CC  
OPEN  
GND  
t
t
t
, t  
PLH PHL  
500Ω  
TEST  
, t  
PZH PHZ  
DUT  
SIGNAL  
V
, t  
PZL PLZ  
I
C
L
500Ω  
Figure 1. AC Test Circuit (C includes probe and jig capacitance)  
L
Test  
Switch  
t
, t  
Open  
PLH PHL  
t
, t  
6V at V = 3.3 ± 0.3V  
CC  
PZL PLZ  
V
x 2 at V = 2.5 ± 0.2V  
CC  
CC  
t
, t  
GND  
PZH PHZ  
V
V
CC  
CC  
OUTPUT  
CONTROL  
DATA  
IN  
V
mi  
V
mi  
GND  
GND  
t
t
t
t
PHZ  
pxx  
pxx  
PZH  
V
V
OH  
Y
DATA  
OUT  
DATA  
OUT  
V
V
mo  
mo  
3-STATE Output High Enable and  
Disable Times for Logic  
Waveform for Inverting and  
Non-Inverting Functions  
t
W
V
CC  
DATA  
V
V
CC  
mi  
CONTROL  
IN  
IN  
V
mi  
GND  
GND  
t
S
t
H
t
rec  
V
CC  
CONTROL  
INPUT  
V
mi  
V
CLOCK  
GND  
mi  
t
S
t
PHL  
t
rec  
t
PLH  
MR  
OR  
CLEAR  
V
mi  
V
mo  
OUTPUT  
V
mo  
Setup Time, Hold Time and  
Recovery Time for Logic  
Propagation Delay, Pulse Width and  
Waveforms  
t
rec  
t
t
f
r
V
CC  
OUTPUT  
V
mi  
CONTROL  
GND  
t
t
PLZ  
PZL  
V
V
OH  
OL  
90%  
90%  
10%  
ANY  
OUTPUT  
DATA  
OUT  
V
mo  
V
X
10%  
V
OL  
3-STATE Output Low Enable and  
Disable Times for Logic  
t
and t  
fall  
rise  
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)  
r
f
V
CC  
Symbol  
3.3V ± 0.3V  
1.5V  
2.7V  
1.5V  
1.5V  
2.5V ± 0.2V  
V
V
V
/ 2  
/ 2  
mi  
CC  
CC  
V
1.5V  
mo  
V
V
+ 0.3V  
− 0.3V  
V
+ 0.3V  
V
+ 0.15V  
− 0.15V  
x
y
OL  
OL  
OL  
V
V
V
− 0.3V  
V
OH  
OH  
OH  
6
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Schematic Diagram (Generic for LCX Family)  
Input Stage  
P2  
P1  
V
CC  
Data  
ESD  
P5  
X1  
D2 N+/P–  
V
DD  
N1  
N2  
P4  
GTO™  
Output  
Input Stage  
D6  
N+/P–  
P3  
N5  
Enable  
N4  
ESD  
D4 N+/P–  
N3  
7
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Tape and Reel Specification  
Tape Format for DQFN  
Package  
Designator  
Tape  
Section  
Number  
Cavities  
Cavity  
Status  
Cover Tape  
Status  
BQX  
Leader (Start End)  
Carrier  
125 (typ)  
3000  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
Trailer (Hub End)  
75 (typ)  
Empty  
Tape Dimensions inches (millimeters)  
Reel Dimensions inches (millimeters)  
Tape Size  
A
B
C
D
N
W1  
W2  
12 mm  
13.0  
(330.0)  
0.059  
(1.50)  
0.512  
(13.00)  
0.795  
(20.20)  
2.165  
(55.00)  
0.488  
(12.4)  
0.724  
(18.4)  
8
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC),  
JEDEC MS-013, 0.300" Wide Package Number M20B  
9
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted  
20-Lead Small Outline Package (SOP),  
EIAJ TYPE II, 5.3mm Wide Package Number M20D  
10  
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted  
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),  
JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B  
11  
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted  
20-Lead Shrink Small Outline Package (SSOP),  
JEDEC MO-150, 5.3mm Wide Package Number MSA20  
12  
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted  
20-Lead Thin Shrink Small Outline Package (TSSOP),  
JEDEC MO-153, 4.4mm Wide Package Number MTC20  
13  
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
FAST®  
FASTr™  
FPS™  
FRFET™  
GlobalOptoisolator™  
GTO™  
ACEx™  
PowerSaver™  
PowerTrench®  
QFET®  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
TCM™  
ISOPLANAR™  
LittleFET™  
MICROCOUPLER™  
MicroFET™  
MicroPak™  
MICROWIRE™  
MSX™  
ActiveArray™  
Bottomless™  
Build it Now™  
CoolFET™  
CROSSVOLT™  
DOME™  
EcoSPARK™  
E2CMOS™  
EnSigna™  
FACT™  
QS™  
QT Optoelectronics™  
Quiet Series™  
RapidConfigure™  
RapidConnect™  
µSerDes™  
ScalarPump™  
SILENT SWITCHER®  
SMART START™  
SPM™  
TinyLogic®  
TINYOPTO™  
TruTranslation™  
UHC™  
HiSeC™  
I2C™  
MSXPro™  
OCX™  
OCXPro™  
UltraFET®  
UniFET™  
VCX™  
i-Lo™  
ImpliedDisconnect™  
IntelliMAX™  
OPTOLOGIC®  
OPTOPLANAR™  
PACMAN™  
POP™  
Wire™  
FACT Quiet Series™  
Across the board. Around the world.™  
The Power Franchise®  
Programmable Active Droop™  
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SuperFET™  
SuperSOT™-3  
Power247™  
PowerEdge™  
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FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY  
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY  
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT  
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NOR THE RIGHTS OF OTHERS.  
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FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. I18  
14  
www.fairchildsemi.com  
74LCX573 Rev. 2.0.0  

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