74LCX646MTCX [FAIRCHILD]
Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs; 低电压八路收发器/寄存器与5V容限输入和输出
| 型号： | 74LCX646MTCX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs |
| 文件： | 总10页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1994
Revised March 2001
74LCX646
Low Voltage Octal Transceiver/Register
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The LCX646 consists of registered bus transceiver circuits,
D-type flip-flops, and control circuitry providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW-to-HIGH
transition of the appropriate pin (CPAB or CPBA) (see
Functional Description).
■ 2.3V − 3.6V VCC specifications provided
■ 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA output drive (VCC = 3.0V)
The LCX646 is designed for low voltage (2.5V or 3.3V) VCC
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
applications with capability of interfacing to a 5V signal
environment.
The LCX646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX646WM
74LCX646MSA
74LCX646MTC
M24B
MSA24
MTC24
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
B0–B7
CPAB, CPBA
SAB, SBA
OE
Transmit/Receive Inputs
Output Enable Input
DIR
Direction Control Input
© 2001 Fairchild Semiconductor Corporation
DS011997
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Logic Symbols
IEEE/IEC
Truth Table
(Note 2)
Inputs
Data I/O
Function
OE
DIR CPAB CPBA SAB SBA A0–A7 B0–B7
H
H
H
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
H or L H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
X
Input
Input
Input Clock An Data into A Register
Clock Bn Data into B Register
X
X
X
X
X
X
X
An to Bn—Real Time (Transparent Mode)
Output Clock An Data into A Register
A Register to Bn (Stored Mode)
L
H or L
H
H
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An—Real Time (Transparent Mode)
Input Clock Bn Data into B Register
B Register to An (Stored Mode)
X
X
X
X
L
L
Output
L
H or L
H
H
L
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Note 2: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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2
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both. The select (SAB, SBA) controls can multiplex stored
and real-time. The examples shown below demonstrate the
four fundamental bus-management functions that can be
performed.
The direction control (DIR) determines which bus will
receive data when OE is LOW. In the isolation mode (OE
HIGH), A data may be stored in one register and/or B data
may be stored in the other register. When an output func-
tion is disabled, the input function is still enabled and may
be used to store and transmit data. Only one of the two
busses, A or B, may be driven at a time.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OE DIR CPAB CPBA SAB SBA
OE
DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
L
H
X
X
L
X
Transfer Storage
Data to A or B
Storage
OE
L
DIR CPAB CPBA SAB SBA
OE
L
DIR CPAB CPBA SAB SBA
L
X
H or L
X
X
H
H
X
H
L
X
L
X
X
X
X
L
L
H
H or L
L
X
X
H
X
X
X
X
X
H
3
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Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 5)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
3.6
5.5
VCC
5.5
±24
±12
±8
Units
VCC
Supply Voltage
Operating
Data Retention
V
V
V
VI
Input Voltage
VO
Output Voltage
HIGH or LOW State
3-STATE
0
0
IOH/IOL
Output Current
VCC = 3.0V − 3.6V
VCC = 2.7V − 3.0V
VCC = 2.3V − 2.7V
mA
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs or I/Os must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 8 mA
VCC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
0.4
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
3-STATE I/O Leakage
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
µA
µA
µA
IOZ
2.3 − 3.6
±5.0
IOFF
Power-Off Leakage Current
VI or VO = 5.5V
0
10
5
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DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
ICC
Parameter
Conditions
Units
(V)
Min
Max
10
Quiescent Supply Current
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 6)
VIH = VCC −0.6V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
µA
µA
±10
500
∆ICC
Increase in ICC per Input
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
CC = 2.7V CC = 2.5V ± 0.2V
L = 50 pF L = 30 pF
Max Min Max
V
CC = 3.3V ± 0.3V
L = 50 pF
Max
V
V
Symbol
Parameter
Units
C
C
C
Min
Min
fMAX
Maximum Clock Frequency
Propagation Delay
Bus to Bus
150
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
MHz
ns
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
7.0
7.0
8.5
8.5
8.5
8.5
8.5
8.5
8.5
8.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
8.0
8.0
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.0
2.0
4.0
8.4
8.4
Propagation Delay
Clock to Bus
10.5
10.5
10.5
10.5
10.5
10.5
10.5
10.5
ns
ns
ns
ns
Propagation Delay
Select to Bus
Output Enable Time
Output Disable Time
Setup Time
ns
ns
ns
tH
Hold Time
tW
Pulse Width
Output to Output Skew
(Note 7)
tOSHL
tOSLH
1.0
1.0
ns
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
TA = 25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
pF
CIN
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
CI/O
CPD
CC = 3.3V, VI = 0V or VCC
pF
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
pF
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6
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
1.5V
VCC/2
V
OL + 0.3V
V
OL + 0.3V
VOL + 0.15V
Vy
V
OH − 0.3V
V
OH − 0.3V
VOH − 0.15V
7
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Schematic Diagram Generic for LCX Family
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8
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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