74LCX86SJX [FAIRCHILD]
Low Voltage Quad 2-Input Exclusive-OR Gate with 5V Tolerant Inputs, 14LD,SOP,EIAJ TYPE II, 5.3MM WIDE, 2000/TAPE REEL;
| 型号： | 74LCX86SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Quad 2-Input Exclusive-OR Gate with 5V Tolerant Inputs, 14LD,SOP,EIAJ TYPE II, 5.3MM WIDE, 2000/TAPE REEL 栅 光电二极管 逻辑集成电路 石英晶振 触发器 |
| 文件： | 总11页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2008
74LCX86
Low Voltage Quad 2-Input Exclusive-OR Gate with 5V
Tolerant Inputs
Features
General Description
■ 5V tolerant inputs
The LCX86 contains four 2-input exclusive-OR gates.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V systems to 3V systems.
■ 2.3V–3.6V V specifications provided
CC
■ 6.5ns t max. (V = 3.3V), 10µA I max.
PD
CC
CC
The 74LCX86 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
■ Power down high impedance inputs and outputs
24mA output drive (V = 3.0V)
■
CC
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500mA
■ ESD performance:
– Machine model > 2000V
– Human model > 200V
Ordering Information
Order
Number
Package
Number
Package Description
74LCX86M
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX86SJ
74LCX86MTC
MTC14
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
Description
A –A
Inputs
Inputs
Outputs
0
3
3
B –B
0
O –O
0
3
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +7.0V
–0.5V to +7.0V
CC
V
DC Input Voltage
I
(1)
V
DC Output Voltage, Output in HIGH or LOW State
–0.5V to V + 0.5V
O
IK
CC
I
DC Input Diode Current, V < GND
–50mA
I
I
DC Output Diode Current
OK
V
< GND
–50mA
+50mA
O
V
> V
CC
O
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50mA
O
I
100mA
CC
I
100mA
GND
T
–65°C to +150°C
STG
Note:
1. I Absolute Maximum Rating must be observed.
O
(2)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Units
V
Supply Voltage
Operating
CC
2.0
1.5
0
3.6
3.6
5.5
V
Data Retention
Input Voltage
V
V
V
I
V
Output Voltage, HIGH or LOW State
Output Current
0
V
CC
O
I
/ I
OH OL
V
V
V
= 3.0V–3.6V
= 2.7V–3.0V
= 2.3V–2.7V
24
12
8
mA
CC
CC
CC
T
Free-Air Operating Temperature
Input Edge Rate, V = 0.8V–2.0V, V = 3.0V
–40
0
85
10
°C
A
∆t / ∆V
ns/V
IN
CC
Note:
2. Unused inputs must be held HIGH or LOW. They may not float.
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
3
DC Electrical Characteristics
T = –40°C to +85°C
A
Symbol
Parameter
V
(V)
Conditions
Min.
1.7
Max.
Units
CC
V
HIGH Level Input Voltage
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
V
IH
2.0
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
V
V
IL
V
I
I
I
I
I
I
I
I
I
I
= –100µA
= –8mA
= –12mA
= –18mA
= –24mA
= 100µA
= 8mA
V
– 0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
1.8
2.2
2.4
2.2
2.7
3.0
V
LOW Level Output Voltage
2.3–3.6
2.3
0.2
0.6
0.4
0.4
0.55
5.0
10
V
OL
2.7
= 12mA
= 16mA
= 24mA
3.0
I
Input Leakage Current
2.3–3.6
0
0 ≤ V ≤ 5.5V
µA
µA
µA
I
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V = 5.5V
I O
OFF
I
2.3–3.6
V = V or GND
10
CC
I
CC
3.6V ≤ V ≤ 5.5V
10
I
∆I
Increase in I per Input
2.3–3.6
V
= V – 0.6V
500
µA
CC
CC
IH
CC
AC Electrical Characteristics
T = –40°C to +85°C, R = 500Ω
A
L
V
= 3.3V 0.3V,
V
= 2.7V,
V = 2.5V 0.2V,
CC
CC
CC
C = 50pF
C = 50pF
C = 30pF
L
L
L
Symbol
Parameter
Propagation Delay
Output to Output Skew
Min.
Max.
6.5
Min.
Max.
Min.
Max.
Units
ns
t
, t
1.5
1.5
7.0
1.5
7.8
PHL PLH
(3)
t
, t
1.0
ns
OSHL OSLH
Note:
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).
OSHL
OSLH
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
4
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.8
Unit
CC
V
Quiet Output Dynamic Peak V
3.3
C = 50pF, V = 3.3V, V = 0V
V
OLP
OL
L
IH
IL
2.5
3.3
2.5
C = 30pF, V = 2.5V, V = 0V
0.6
L
IH
IL
V
Quiet Output Dynamic Valley V
C = 50pF, V = 3.3V, V = 0V
–0.8
–0.6
V
OLV
OL
L
IH
IL
C = 30pF, V = 2.5V, V = 0V
L
IH
IL
Capacitance
Symbol
Parameter
Conditions
Typical
Units
pF
C
Input Capacitance
V
= Open, V = 0V or V
CC
7
8
IN
CC
CC
CC
I
C
Output Capacitance
V
V
= 3.3V, V = 0V or V
CC
pF
OUT
I
C
Power Dissipation Capacitance
= 3.3V, V = 0V or V , f = 10MHz
25
pF
PD
I
CC
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
5
AC Loading and Waveforms (Generic for LCX Family)
Test
Switch
t
t
, t
Open
PLH PHL
, t
6V at V = 3.3 0.3V
PZL PLZ
CC
V
x 2 at V = 2.5 0.2V
CC
CC
t
, t
GND
PZH PHZ
Figure 1. AC Test Circuit (C includes probe and jig capacitance)
L
3-STATE Output Low Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and t Waveforms
rec
3-STATE Output High Enable and
Disable Times for Logic
t
and t
fall
rise
V
CC
Symbol
3.3V 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V 0.2V
V
V
V
/ 2
/ 2
mi
CC
CC
V
1.5V
mo
V
V
+ 0.3V
– 0.3V
V
+ 0.3V
V
+ 0.15V
– 0.15V
x
y
OL
OL
OL
V
V
V
– 0.3V
V
OH
OH
OH
Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns)
r
f
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
6
Schematic Diagram (Generic for LCX Family)
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
7
Physical Dimensions
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
1.70
1.27
1
7
PIN ONE
INDICATOR
0.51
0.35
1.27
(0.33)
LAND PATTERN RECOMMENDATION
M
0.25
C B A
1.75 MAX
SEE DETAIL A
1.50
1.25
0.25
0.19
0.25
0.10
C
0.10
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.50
0.25
X 45°
R0.10
R0.10
GAGE PLANE
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE: 20:1
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
9
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
6.10
0.45
12.00°
TOP & BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
R0.09min
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
Figure 5. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
10
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SupreMOS™
FPS™
Power220®
SyncFET™
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
®
Global Power ResourceSM
Green FPS™
Green FPS™e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
FAST®
Ultra FRFET™
UniFET™
VCX™
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1995 Fairchild Semiconductor Corporation
74LCX86 Rev. 1.5.0
www.fairchildsemi.com
11
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