74LCXZ245 [FAIRCHILD]
Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs; 低电压双向收发器，具有5V容限输入和输出
| 型号： | 74LCXZ245 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2000
Revised October 2000
74LCXZ245
Low Voltage Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
Features
■ 5V tolerant inputs and outputs
The 74LCXZ245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is designed for low voltage
(2.5V and 3.3V) VCC applications with capability of interfac-
■ 2.3V–3.6V VCC specifications provided
■ 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ ±24 mA output drive (VCC = 3.0V)
ing to a 5V signal environment. The T/R input determines
the direction of data flow through the device. The OE input
disables both the A and B ports by placing them in a high
impedance state.
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The 74LCXZ245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation. When VCC is between 0V
and 1.5V, the 74LCXZ245 is on the high impedance state
during power up or power down. This places the outputs in
the high impedance (Z) state preventing intermittent low
impedance loading or glitching in bus oriented applications.
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCXZ245WM
74LCXZ245SJ
74LCXZ245MSA
74LCXZ245MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MSA20
MTC20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
Transmit/Receive Input
T/R
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2000 Fairchild Semiconductor Corporation
DS500362
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Truth Table
Inputs
Outputs
OE
L
T/R
L
Bus B0 – B7 Data to Bus A0 – A7
L
H
Bus A0 – A7 Data to Bus B0 – B7
HIGH Z State on A0 – A7, B0 – B7 (Note 2)
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Note 2: Unused bus terminals during HIGH Z State must be held HIGH or LOW.
Logic Diagram
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2
Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
Conditions
Units
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4)
IIK
DC Input Diode Current
DC Output Diode Current
−50
−50
VI < GND
mA
mA
IOK
V
V
O < GND
O > VCC
+50
IO
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±50
mA
mA
mA
°C
ICC
±100
IGND
TSTG
±100
−65 to +150
Recommended Operating Conditions (Note 5)
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
VCC
5.5
±24
±12
±8
Units
Supply Voltage
Input Voltage
Output Voltage
Operating
V
V
VI
VO
HIGH or LOW State
3-STATE
0
V
0
IOH/IOL
Output Current
VCC = 3.0V − 3.6V
V
CC = 2.7V - 3.0V
CC = 2.3V - 2.7V
mA
V
TA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V
0
10
ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs or I/O pins must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
TA = −40°C to +85°C
Symbol
VIH
Parameter
Conditions
Units
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 - 3.6
2.3 - 3.6
2.3
Min
1.7
2.0
Max
HIGH Level Input Voltage
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
VOH
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OL = 100 µA
OL = 8mA
VCC − 0.2
1.8
2.7
2.2
V
V
3.0
2.4
3.0
2.2
VOL
LOW Level Output Voltage
2.3 − 3.6
2.3
0.2
0.6
OL = 12 mA
OL = 16 mA
OL = 24 mA
2.7
0.4
3.0
0.4
3.0
0.55
±5.0
II
Input Leakage Current
3-STATE I/O Leakage
0 ≤ VI ≤ 5.5V
0 ≤ VO ≤ 5.5V
VI = VIH or VIL
2.3 − 3.6
µA
µA
µA
µA
IOZ
2.3 − 3.6
0
±5.0
10
IOFF
Power-Off Leakage Current
Power Up/ Power Down
3-STATE Output Current
VI or VO = 5.5V
O = to VCC
VI = VCC or GND
IPU/PD
V
0 − 1.5
±5.0
3
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DC Electrical Characteristics (Continued)
VCC
TA = −40°C to +85°C
Symbol
ICC
Parameter
Conditions
Units
(V)
Min
Max
225
Quiescent Supply Current
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 6)
VIH = VCC −0.6V
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
µA
µA
±225
500
∆ICC
Increase in ICC per Input
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A = −40°C to +85°C, RL = 500Ω
CC = 3.3V ± 0.3V CC = 2.7V
L = 50 pF L = 50 pF
Max
V
V
Symbol
Parameter
Units
C
C
Min
Min
Max
8.0
8.0
9.5
9.5
8.5
8.5
tPHL
tPLH
tPZL
tPZH
tPLZ
Propagation Delay
An to Bn or Bn to An
Output Enable Time
1.5
1.5
1.5
1.5
1.5
1.5
7.0
7.0
8.5
8.5
7.5
7.5
1.0
1.0
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
Output Disable Time
tPHZ
tOSHL
tOSLH
Output to Output Skew
(Note 7)
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
T
A = 25°C
VCC
(V)
Symbol
VOLP
Parameter
Conditions
Units
Typical
0.8
Quiet Output Dynamic Peak VOL
C
C
C
C
L = 50 pF, VIH = 3.3V, VIL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
L = 50 pF, VIH = 3.3V, V IL = 0V
L = 30 pF, VIH = 2.5V, VIL = 0V
3.3
2.5
3.3
2.5
V
V
0.6
VOLV
Quiet Output Dynamic Valley VOL
−0.8
−0.6
Capacitance
Symbol
Parameter
Conditions
CC = Open, VI = 0V or VCC
Typical
Units
CIN
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
V
V
V
7
8
pF
pF
pF
CI/O
CPD
CC = 3.3V, VI = 0V or VCC
CC = 3.3V, VI = 0V or VCC, f = 10 MHz
25
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4
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
PZL, tPLZ
Switch
Open
t
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
tPZH,tPHZ
GND
3-STATE Output High Enable and
Waveform for Inverting and Non-Inverting Functions
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and trec Waveforms
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
VCC
Symbol
3.3V ± 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V ± 0.2V
VCC/2
Vmi
Vmo
Vx
1.5V
VCC/2
V
V
OL + 0.3V
OH − 0.3V
V
V
OL + 0.3V
V
V
OL + 0.15V
OH − 0.15V
Vy
OH − 0.3V
5
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Schematic Diagram Generic for LCX Family
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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