74LVQ00SJ [FAIRCHILD]
Low Voltage Quad 2-Input NAND Gate; 低电压四2输入与非门型号: | 74LVQ00SJ |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Low Voltage Quad 2-Input NAND Gate |
文件: | 总5页 (文件大小:56K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
February 1992
Revised April 2001
74LVQ00
Low Voltage Quad 2-Input NAND Gate
General Description
The LVQ00 contains four 2-input NAND gates.
Features
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Guaranteed incident wave switching into 75Ω
Ordering Code:
Order Number
74LVQ00SC
74LVQ00SJ
Package Number
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M14D
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn
Description
Inputs
Outputs
On
© 2001 Fairchild Semiconductor Corporation
DS011341
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
2.0V to 3.6V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
VO = VCC + 0.5V
VCC @ 3.0V
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Voltage (VO)
−0.5V to VCC + 0.5V
±50 mA
DC Output Source or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND
Storage Temperature (TSTG
DC Latch-Up Source or Sink Current
)
±200 mA
−65°C to +150°C
±100 mA
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
)
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
Typ
Guaranteed Limits
Minimum High Level
Input Voltage
V
OUT = 0.1V
3.0
1.5
2.0
2.0
V
V
or VCC − 0.1V
VIL
Maximum Low Level
Input Voltage
V
OUT = 0.1V
3.0
3.0
3.0
3.0
3.0
1.5
0.8
2.9
0.8
2.9
or VCC − 0.1V
IOUT = −50 µA
VOH
Minimum High Level
Output Voltage
2.99
V
V
VIN = VIL or VIH
2.58
0.1
2.48
0.1
I
I
OH = −12 mA (Note 3)
OUT = 50 µA
VOL
Maximum Low Level
Output Voltage
0.002
V
IN = VIL or VIH
0.36
0.44
I
OL = 12 mA (Note 3)
IIN
Maximum Input
3.6
±0.1
±1.0
µA
mA
µA
V
VI = VCC, GND
Leakage Current
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
3.6
3.6
36
V
V
V
OLD = 0.8V Max (Note 5)
OHD = 2.0V Min (Note 5)
IN = VCC
−25
3.6
3.3
3.3
3.3
3.3
2.0
1.0
20.0
or GND
VOLP
VOLV
VIHD
VILD
Quiet Output
0.6
−0.5
1.5
(Note 6)(Note 7)
Maximum Dynamic VOL
Quiet Output
−1.0
2.0
V
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
V
1.5
0.8
V
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f = 1 MHz.
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2
AC Electrical Characteristics
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
VCC
C
L = 50 pF
C
Symbol
Parameter
Units
(V)
2.7
Min
2.0
2.0
1.5
1.5
Typ
8.4
7.0
6.6
5.5
1.0
1.0
Max
13.4
9.5
Min
tPLH
Propagation Delay
2.0
2.0
1.0
1.0
14.0
10.0
12.0
8.5
ns
ns
ns
3.3 ± 0.3
2.7
tPHL
Propagation Delay
11.3
8.0
3.3 ± 0.3
2.7
tOSHL,
tOSLH
Output to Output Skew
(Note 9)
1.5
1.5
3.3 ± 0.3
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
PD (Note 10) Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
Parameter
Typ
4.5
22
Units
pF
Conditions
Input Capacitance
V
CC = Open
CC = 3.3V
C
pF
V
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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which, (a) are intended for surgical implant into the
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instructions for use provided in the labeling, can be rea-
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user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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