74LVT373MTC [FAIRCHILD]
Low Voltage Octal Transparent Latch with 3-STATE Outputs; 低电压八路透明锁存器带3态输出
| 型号： | 74LVT373MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1999
Revised October 1999
74LVT373 • 74LVTH373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH373), also
available without bushold feature (74LVT373).
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
The LVTH373 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
■ Outputs source/sink −32 mA/+64 mA
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
■ Functionally compatible with the 74 series 373
interface to a 5V environment. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Ordering Code:
Order Number Package Number
Package Description
74LVT373WM
74LVT373SJ
M20B
M20D
MTC20
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20D
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS012015
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Connection Diagram
Pin Descriptions
Pin Names
Description
Data Inputs
Latch Enable Input
D0–D7
LE
OE
Output Enable Input
O0–O7
3-STATE Latch Outputs
Truth Table
Inputs
OE
Outputs
LE
Dn
On
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
= Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Functional Description
The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters the
ing the HIGH-to-LOW transition of LE. The 3-STATE
standard outputs are controlled by the Output Enable (OE)
input. When OE is LOW, the standard outputs are in the 2-
state mode. When OE is HIGH, the standard outputs are in
the high impedance mode but this does not interfere with
entering new data into the latches.
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its
changes. When LE is LOW, the latches store the informa-
tion that was present on the D inputs a setup time preced-
D input
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Symbol
VCC
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
VI
DC Input Voltage
V
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 2)
V
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
−32
64
Units
V
Supply Voltage
VI
Input Voltage
V
IOH
IOL
TA
HIGH Level Output Current
LOW Level Output Current
mA
mA
°C
Free-Air Operating Temperature
−40
85
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: I Absolute Maximum Rating must be observed.
O
3
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DC Electrical Characteristics
T
= −40°C to +85°C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 3)
V
V
V
V
Input Clamp Diode Voltage
Input HIGH Voltage
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
−1.2
V
I = −18 mA
IK
I
2.0
V
≤ 0.1V or
IH
IL
O
O
V
Input LOW Voltage
0.8
V
≥ V − 0.1V
CC
Output HIGH Voltage
V
− 0.2
V
V
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 64 mA
OH
CC
OH
OH
OH
OL
OL
OL
OL
OL
2.4
3.0
2.0
V
V
Output LOW Voltage
2.7
0.2
0.5
V
OL
2.7
V
3.0
0.4
V
3.0
0.5
V
3.0
0.55
V
I
Bushold Input Minimum Drive
3.0
75
−75
500
−500
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V = 0.8V
I
I(HOLD)
(Note 4)
V = 2.0V
I
I
Bushold Input Over-Drive
Current to Change State
3.0
(Note 5)
(Note 6)
I(OD)
(Note 4)
I
Input Current
3.6
3.6
3.6
10
±1
V = 5.5V
I
I
Control Pins
Data Pins
V = 0V or V
I CC
−5
V = 0V
I
1
V = V
I CC
I
I
Power Off Leakage Current
Power up/down 3-STATE
Output Current
0
±100
±100
0V ≤ V or V ≤ 5.5V
I O
OFF
0–1.5V
V = 0.5V to 3.0V
O
PU/PD
V = GND or V
I
CC
I
I
I
I
I
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
3.6
−5
5
µA
µA
V
V
V
= 0.5V
= 3.0V
OZL
OZH
O
O
+
10
µA
< V ≤ 5.5V
CC O
OZH
0.19
5
mA
mA
mA
mA
Outputs HIGH
Outputs LOW
CCH
CCL
CCZ
Power Supply Current
Power Supply Current
0.19
0.19
Outputs Disabled
+
Power Supply Current
V
≤ V ≤ 5.5V,
CCZ
CC O
Outputs Disabled
One Input at V − 0.6V
∆I
Increase in Power Supply Current
(Note 7)
3.6
0.2
mA
CC
CC
Other Inputs at V or GND
CC
Note 3: All typical values are at V = 3.3V, T = 25°C.
CC
A
Note 4: Applies to Bushold versions only (74LVTH373).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 8)
T
= 25°C
Conditions
A
V
(V)
CC
C
= 50 pF
Symbol
Parameter
Units
L
Min
Typ
Max
R
= 500Ω
L
V
V
Quiet Output Maximum Dynamic V
3.3
3.3
0.8
V
V
(Note 9)
(Note 9)
OLP
OL
Quiet Output Minimum Dynamic V
−0.8
OLV
OL
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
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4
AC Electrical Characteristics
T
= −40°C to +85°C
A
C
= 50 pF, R = 500Ω
L
L
Symbol
Parameter
Units
V
= 3.3V ±0.3V
V
= 2.7V
CC
CC
Typ
(Note 10)
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
to O
1.5
1.5
1.7
1.7
1.3
1.3
1.9
1.9
3.0
1.1
1.4
4.5
4.5
4.6
4.5
4.8
4.8
4.6
4.6
1.5
1.5
1.7
1.7
1.3
1.3
1.9
1.9
3.0
1.0
1.4
5.0
4.9
4.9
5.0
5.9
5.5
4.9
4.9
PHL
ns
ns
ns
ns
D
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
W
n
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
LE Pulse Width
ns
ns
ns
Setup Time, D to LE
S
n
Hold Time, D to LE
H
n
Note 10: All typical values are at V = 3.3V, T = 25°C.
CC
A
Capacitance (Note 11)
Symbol
Parameter
Conditions
Typical
Units
C
Input Capacitance
Output Capacitance
V
V
= OPEN, V = 0V or V
CC
3
5
pF
pF
IN
CC
CC
I
C
= 3.0V, V = 0V or V
O CC
OUT
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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相关型号：
74LVT373SJX
Bus Driver, LVT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
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