74LVTH162244MEA [FAIRCHILD]
Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25? Series Resistors in the Outputs; 低电压16位缓冲器/线与3态输出和25个驱动器？串联电阻的输出
| 型号： | 74LVTH162244MEA |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25? Series Resistors in the Outputs |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
Revised June 2005
74LVT162244 • 74LVTH162244
Low Voltage 16-Bit Buffer/Line Driver
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT162244 and LVTH162244 contain sixteen non-
inverting buffers with 3-STATE outputs designed to be
employed as a memory and address driver, clock driver, or
bus oriented transmitter/receiver. The device is nibble con-
trolled. Individual 3-STATE control inputs can be shorted
together for 8-bit or 16-bit operation.
5V VCC
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162244),
also available without bushold feature (74LVT162244).
■ Live insertion/extraction permitted
The LVT162244 and LVTH162244 are designed with
equivalent 25 series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
■ Power Up/Power Down high impedance provides glitch-
free bus loading
■ Outputs include equivalent series resistance of 25 to
make external termination resistors unnecessary and
reduce overshoot and undershoot
The LVTH162244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Functionally compatible with the 74 series 162244
■ Latch-up performance exceeds 500 mA
■ ESD performance:
These buffers and line drivers are designed for low-voltage
(3.3V) VCC applications, but with the capability to provide a
Human-body model 2000V
TTL interface to a 5V environment. The LVT162244 and
LVTH162244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Machine model 200V
Charged-device 1000V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Package
Order Number
Package Description
Number
74LVT162244G
(Note 1)(Note 2)
BGA54A
MS48A
MTD48
BGA54A
MS48A
MS48A
MTD48
MTD48
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162244MEA
(Note 2)
74LVT162244MTD
(Note 2)
74LVTH162244G
(Note 1)(Note 2)
74LVTH162244MEA
74LVTH162244MEX
74LVTH162244MTD
74LVTH162244MTX
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tube]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tape and Reel]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tube]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tape and Reel]
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS012445
www.fairchildsemi.com
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Inputs (Active LOW)
I0–I15
O0–O15
NC
Inputs
Outputs
No Connect
FBGA Pin Assignments
Connection Diagrams
1
2
3
4
5
6
Pin Assignment for SSOP and TSSOP
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
OE2
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE4
OE3
NC
I15
Truth Table
Inputs
Outputs
OE1
I0–I3
O0–O3
L
L
L
H
X
L
H
Z
H
OE2
I4–I7
O4–O7
L
L
L
H
X
L
H
Z
H
OE3
I8–I11
O8–O11
L
L
L
H
X
L
H
Z
Pin Assignment for FBGA
H
OE4
I12–I15
O12–O15
L
L
L
H
X
L
H
Z
H
H
Z
HIGH Voltage Level
High Impedance
L
X
LOW Voltage Level
Immaterial
(Top Thru View)
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2
Functional Description
The LVT162244 and LVTH162244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagram
3
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Absolute Maximum Ratings(Note 3)
Symbol
VCC
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
V
VI
DC Input Voltage
Output Voltage
VO
Output in 3-STATE
V
Output in HIGH or LOW State (Note 4)
VI GND
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
12
Units
Supply Voltage
Input Voltage
V
V
VI
IOH
IOL
TA
HIGH-Level Output Current
mA
mA
C
LOW-Level Output Current
12
Free Air Operating Temperature
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
40
0
85
t/ V
10
ns/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
2.7
Min
Max
V
V
V
V
Input Clamp Diode Voltage
1.2
V
V
V
I
18 mA
0.1V or
IK
I
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.0
V
V
IH
IL
O
0.8
V
0.1V
A
O
CC
V
0.2
I
I
I
I
100
OH
CC
OH
OH
OL
OL
V
V
A
A
2.0
12 mA
100
V
Output LOW Voltage
2.7
0.2
0.8
A
OL
3.0
12 mA
0.8V
I
Bushold Input Minimum Drive
75
75
V
V
I(HOLD)
I
I
3.0
3.0
(Note 5)
2.0V
I
Bushold Input Over-Drive
Current to Change State
Input Current
500
500
(Note 6)
(Note 7)
I(OD)
(Note 5)
I
3.6
3.6
10
1
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
I
Control Pins
Data Pins
CC
A
5
3.6
0
1
V
CC
I
I
Power Off Leakage Current
Power Up/Down
100
A
A
0V V or V
5.5V
OFF
I
O
V
V
V
V
V
0.5V to 3.0V
PU/PD
O
I
0–1.5V
100
3-STATE Current
GND or V
0.5V
CC
I
I
I
I
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
5
5
A
A
OZL
OZH
OZH
CCH
CCL
CCZ
O
O
CC
3.0V
10
A
V
5.5V
O
0.19
5
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
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4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
Min Max
CC
A
Symbol
Parameter
Power Supply Current
Units
mA
Conditions
(V)
I
V
V
5.5V,
Outputs Disabled
One Input at V
CCZ
CC
O
3.6
0.19
0.2
I
Increase in Power Supply Current
(Note 8)
0.6V
CC
CC
3.6
mA
Other Inputs at V or GND
CC
Note 5: Applies to bushold versions only (74LVTH162244).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 9)
V
T
25 C
Typ
Conditions
CC
A
Symbol
Parameter
Units
C
50 pF, R
500
(V)
3.3
3.3
Min
Max
L
L
V
V
Quiet Output Maximum Dynamic V
0.8
0.8
V
V
(Note 10)
(Note 10)
OLP
OL
Quiet Output Minimum Dynamic V
OLV
OL
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
40 C to 85 C, C
3.3V 0.3V
Max
50 pF, R
L
500
2.7V
A
L
V
V
CC
CC
Symbol
Parameter
Units
Min
Min
Max
t
t
t
t
t
t
t
t
Propagation Delay Data to Output
Output Enable Time
1.4
1.2
1.2
1.4
2.0
1.5
4.0
3.7
5.1
5.4
5.0
5.0
1.4
1.2
1.2
1.4
2.0
1.5
4.8
4.1
6.5
6.9
5.4
5.4
PLH
ns
ns
ns
ns
PHL
PZH
PZL
Output Disable Time
PHZ
PLZ
Output to Output Skew
(Note 11)
OSHL
OSLH
1.0
1.0
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Capacitance (Note 12)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Typical
Units
pF
C
C
V
V
0V, V 0V or V
4
8
IN
CC
I
CC
3.0V, V
0V or V
CC
pF
OUT
CC
O
Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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