74LVTH162374MTX [FAIRCHILD]
Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs; 低电压16位D型触发器带3态输出和25ヘ系列电阻的输出
| 型号： | 74LVTH162374MTX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25з Series Resistors in the Outputs |
| 文件： | 总8页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2000
Revised June 2005
74LVTH162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVTH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Power Down high impedance provides
glitch-free bus loading
The LVTH162374 is designed with equivalent 25 series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
■ Outputs include equivalent series resistance of 25 to
make external termination resistors unnecessary and
reduce overshoot and undershoot
■ Functionally compatible with the 74 series 16374
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH162374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) VCC
Human-body model 2000V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Machine model 200V
Charged-device model 1000V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Package
Order Number
Package Description
Number
74LVTH162374GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LVTH162374MEA
74LVTH162374MEX
74LVTH162374MTD
74LVTH162374MTX
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500355
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
Pin Descriptions
Pin Names
Description
Pin Assignments for SSOP and TSSOP
OEn
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
CPn
I0–I15
O0–O15
NC
3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
CP1
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
Pin Assignment for FBGA
L
L
H
L
H
L
L
L
X
X
Oo
Z
X
H
Inputs
OE2
Outputs
O8–O15
CP2
I8–I15
L
L
H
L
H
L
L
L
X
X
Oo
Z
X
H
H
L
X
Z
O
HIGH Voltage Level
LOW Voltage Level
Immaterial
(Top Thru View)
HIGH Impedance
Previous O before HIGH-to-LOW of CP
o
o
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2
Functional Description
The LVTH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The
device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the
Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 2)
Symbol
VCC
VI
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
V
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
VI GND
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
12
Units
Supply Voltage
Input Voltage
V
V
VI
IOH
IOL
TA
HIGH Level Output Current
mA
mA
C
LOW Level Output Current
12
Free-Air Operating Temperature
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
40
85
t/ V
0
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
2.7
Min
Max
V
V
V
V
Input Clamp Diode Voltage
1.2
V
V
V
I
18 mA
0.1V or
IK
I
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.0
V
V
IH
IL
O
O
0.8
0.2
V
0.1V
A
CC
V
I
I
I
I
100
OH
CC
OH
OH
OL
OL
V
V
A
A
2.0
12 mA
100
V
Output LOW Voltage
2.7
0.2
0.8
A
OL
3.0
12 mA
0.8V
I
I
I
Bushold Input Minimum Drive
3.0
75
75
V
V
I(HOLD)
I(OD)
I
I
I
2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
500
500
(Note 4)
(Note 5)
3.0
3.6
3.6
10
1
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
Control Pins
Data Pins
CC
A
5
3.6
0
1
V
CC
I
I
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
100
A
A
0V V or V
5.5V
OFF
I
O
V
V
V
V
V
0.5V to 3.0V
PU/PD
O
I
0–1.5V
100
GND or V
0.5V
CC
I
I
I
I
I
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
3.6
5
5
A
A
OZL
OZH
OZH
CCH
CCL
CCZ
O
O
CC
3.0V
10
A
V
5.5V
O
0.19
5
mA
mA
mA
Outputs HIGH
Outputs LOW
Power Supply Current
Power Supply Current
0.19
Outputs Disabled
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4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Power Supply Current
Units
Conditions
(V)
Min
Max
I
3.6
0.19
mA
V
V
O
5.5V,
CCZ
CC
Outputs Disabled
One Input at V
I
Increase in Power Supply Current
(Note 6)
3.6
0.2
mA
0.6V
CC
CC
Other Inputs at V or GND
CC
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 7)
V
T
25 C
Conditions
CC
A
Symbol
Parameter
Units
C
50 pF, R
500
(V)
3.3
3.3
Min
Typ
Max
L
L
V
V
Quiet Output Maximum Dynamic V
0.8
0.8
V
V
(Note 8)
(Note 8)
OLP
OL
Quiet Output Minimum Dynamic V
OLV
OL
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
40 C to 85 C, C
3.3V 0.3V
Max
50 pF, R
L
500
A
L
Symbol
Parameter
V
V
2.7V
Units
CC
CC
Min
160
2.0
1.6
1.8
1.2
1.9
2.0
1.8
0.8
3.0
Min
Max
f
t
t
t
t
t
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
150
2.0
1.6
1.8
1.2
1.9
2.0
2.0
0.1
3.0
MHz
ns
MAX
5.1
5.3
5.0
5.6
5.0
5.4
5.3
6.2
6.0
6.9
5.1
5.7
PHL
PLH
PZL
PZH
PLZ
PHZ
S
CP to O
n
Output Enable Time
ns
ns
Output Disable Time
Setup Time
Hold Time
ns
ns
ns
H
Pulse Width
W
Output to Output Skew (Note 9)
1.0
1.0
1.0
1.0
OSHL
OSLH
ns
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
Capacitance (Note 10)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
OPEN, V 0V or V
CC
Typical
Units
pF
C
C
V
V
4
8
IN
CC
I
3.0V, V
0V or V
CC
pF
OUT
CC
O
Note 10: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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