74LVTH16543 [FAIRCHILD]
Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs; 低电压16位寄存收发器与3态输出
| 型号： | 74LVTH16543 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
Revised October 2001
74LVT16543 • 74LVTH16543
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT16543 and LVTH16543 16-bit transceivers
contain two sets of D-type latches for temporary storage of
data flowing in either direction. Separate Latch Enable and
Output Enable inputs are provided for each register to per-
mit independent control of inputting and outputting in either
direction of data flow. Each byte has separate control
inputs, which can be shorted together for full 16-bit opera-
tion.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16543)
■ Also available without bushold feature (74LVT16543)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
The LVTH16543 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16543
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
These transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to
a 5V environment. The LVT16543 and
Human-body model > 2000V
LVTH16543 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Machine model > 200V
Charged-device model > 1000V
Ordering Code:
Order Number
Package Number
Package Description
74LVT16543MEA
(Preliminary)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16543MTD
(Preliminary)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16543MEA
74LVTH16543MTD
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS012449
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Connection Diagram
Pin Descriptions
Pin
Description
Names
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
Functional Description
The LVT16543 and LVTH16543 contain two sets of D-type
latches, with separate input and output controls for each.
For data flow from A to B, for example, the A to B Enable
(CEAB) input must be LOW in order to enter data from the
A Port or take data from the B Port as indicated in the Data
I/ O Control Table. With CEAB LOW, a low signal on
(LEAB) input makes the A to B latches transparent; a sub-
sequent LOW-to-HIGH transition of the LEAB line puts the
A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both
LOW, the B output buffers are active and reflect the data
present on the output of the A latches. Control of data flow
from B to A is similar, but using the CEBA, LEBA and
OEBA. Each byte has separate control inputs, allowing the
device to be used as two 8-bit transceivers or as one 16-bit
transceiver.
Data I/O Control Table
Inputs
Latch Status
(Byte n)
Output
Buffers
(Byte n)
CEABn
LEABn
OEABn
H
X
L
X
H
L
X
X
X
H
L
Latched
Latched
Transparent
—
High Z
—
—
X
L
X
X
High Z
Driving
—
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
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2
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 1)
Symbol
VCC
Parameter
Supply Voltage
Value
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−50
Conditions
Units
V
VI
DC Input Voltage
V
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 2)
V
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
VI < GND
mA
mA
−50
V
V
V
O < GND
64
O > VCC Output at HIGH State
O > VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
±64
mA
mA
°C
IGND
TSTG
±128
−65 to +150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
−32
64
Units
Supply Voltage
V
V
VI
Input Voltage
IOH
IOL
TA
HIGH-Level Output Current
LOW-Level Output Current
mA
Free-Air Operating Temperature
−40
85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0
10
ns/V
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: IO Absolute Maximum Rating must be observed.
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4
DC Electrical Characteristics
VCC
T A = −40°C to +85°C
Symbol
Parameter
Units
Conditions
II = −18 mA
(V)
2.7
Min
Max
VIK
Input Clamp Diode Voltage
Input HIGH Voltage
−1.2
V
V
VIH
VIL
2.7–3.6
2.7–3.6
2.7–3.6
2.7
2.0
V
O ≤ 0.1V or
O ≥ VCC − 0.1V
Input LOW Voltage
0.8
V
VOH
Output HIGH Voltage
V
CC − 0.2
2.4
V
V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
3.0
2.0
V
VOL
Output LOW Voltage
2.7
0.2
0.5
V
2.7
V
3.0
0.4
V
3.0
0.5
V
3.0
0.55
V
II(HOLD)
(Note 3)
II(OD)
Bushold Input Minimum Drive
75
−75
µA
µA
µA
µA
µA
µA
µA
µA
µA
VI = 0.8V
3.0
3.0
VI = 2.0V
Bushold Input Over-Drive
Current to Change State
Input Current
500
(Note 4)
(Note 3)
II
−500
(Note 5)
3.6
3.6
10
±1
VI = 5.5V
Control Pins
Data Pins
VI = 0V or VCC
VI = 0V
−5
3.6
0
1
VI = VCC
IOFF
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
±100
0V ≤ VI or VO ≤ 5.5V
IPU/PD
VO = 0.5V to 3.0V
0–1.5V
±100
µA
VI = GND or VCC
IOZL (Note 3) 3-STATE Output Leakage Current
IOZL 3-STATE Output Leakage Current
OZH (Note 3) 3-STATE Output Leakage Current
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
−5
−5
µA
µA
V
V
V
V
O = 0.0V
O = 0.5V
O = 3.6V
O = 3.0V
I
5
µA
IOZH
IOZH
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
5
µA
+
10
µA
VCC < VO ≤ 5.5V
ICCH
ICCL
ICCZ
0.19
5
mA
mA
mA
mA
Outputs HIGH
Power Supply Current
Outputs LOW
Power Supply Current
0.19
0.19
Outputs Disabled
VCC ≤ VO ≤ 5.5V,
Outputs Disabled
One Input at VCC − 0.6V
Other Inputs at VCC or GND
ICCZ
+
Power Supply Current
∆ICC
Increase in Power Supply Current
(Note 6)
3.6
0.2
mA
Note 3: Applies to bushold versions only (74LVTH16543)
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 7)
VCC
T
A = 25°C
Conditions
Symbol
Parameter
Units
C
L = 50 pF, RL = 500Ω
(V)
3.3
3.3
Min
Typ
0.8
Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
V
V
(Note 8)
(Note 8)
−0.8
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW.
5
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AC Electrical Characteristics
T
A = −40°C to +85°C
L = 50 pF, RL = 500 Ω
CC = 3.3 ± 0.3V CC = 2.7V
C
Symbol
Parameter
Units
V
V
Min
Max
4.2
4.4
4.7
5.1
4.7
5.1
5.5
4.9
4.6
5.0
5.5
4.9
Min
1.2
1.2
1.3
1.3
1.3
1.3
2.0
2.0
1.3
1.3
2.0
2.0
Max
4.5
4.9
5.5
5.8
5.4
6.1
5.7
4.9
5.6
6.1
5.8
4.9
tPLH
Propagation Delay
Data to Outputs
Propagation Delay
LE to A or B
1.2
1.2
1.3
1.3
1.3
1.3
2.0
2.0
1.3
1.3
2.0
2.0
ns
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OE to A or B
Output Disable Time
OE to A or B
Output Enable Time
CE to A or B
Output Disable Time
CE to A or B
ns
ns
tW
tS
Pulse Duration
Setup Time
LE LOW
3.3
0.5
0.8
0.5
0.6
1.5
1.2
1.7
1.6
3.3
0.5
1.3
0.0
1.1
0.7
1.3
0.9
1.8
A or B before LE, Data HIGH
A or B before LE, Data LOW
A or B before CE, Data HIGH
A or B before CE, Data LOW
A or B after LE, Data HIGH
A or B after LE, Data LOW
A or B after CE, Data HIGH
A or B after CE, Data LOW
ns
tH
Hold Time
ns
ns
tOSLH
tOSHL
Output to Output Skew (Note 9)
1.0
1.0
1.0
1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
CIN
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
CC = OPEN, VI = 0V or VCC
CC = 3.0V, VO = 0V or VCC
Typical
Units
pF
V
V
4
8
pF
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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6
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS56A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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