74LVTH574MTC [FAIRCHILD]
Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs; 低电压八路D型触发器带3态输出
| 型号： | 74LVTH574MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
Revised March 2005
74LVT574 • 74LVTH574
Low Voltage Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT574 and LVTH574 are high-speed, low-power
octal D-type flip-flop featuring separate D-type inputs for
each flip-flop and 3-STATE outputs for bus-oriented appli-
cations. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH574),
also available without bushold feature (74LVT574)
The LVTH574 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
■ Outputs source/sink 32 mA/ 64 mA
■ Functionally compatible with the 74 series 574
■ Latch-up performance exceeds 500 mA
■ ESD performance:
interface to a 5V environment. The LVT574 and LVTH574
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Human-body model 2000V
Machine model 200V
Charged-device model 1000V
Ordering Code:
Package
Order Number
Package Description
Number
74LVT574WM
74LVT574SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVT574MSA
74LVT574MTC
MSA20
MTC20
MTC20
74LVT574MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH574WM
74LVTH574SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH574MSA
74LVTH574MTC
MSA20
MTC20
MTC20
74LVTH574MTCX_NL
(Note 1)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS012451
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Logic Symbols
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
IEEE/IEC
Truth Table
Inputs
Outputs
Dn
H
L
CP
OE
L
On
H
L
L
X
L
L
Oo
Z
X
X
H
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
Previous O before HIGH to LOW of CP
Connection Diagram
O
o
o
Functional Description
The LVT574 and LVTH574 consist of eight edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The buffered clock and buffered Output Enable
are common to all flip-flops. The eight flip-flops will store
the state of their individual D-type inputs that meet the
setup and hold time requirements on the LOW-to-HIGH
Clock (CP) transition. With the Output Enable (OE) LOW,
the contents of the eight flip-flops are available at the out-
puts. When the OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Symbol
VCC
Parameter
Supply Voltage
Value
0.5 to 4.6
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
50
Conditions
Units
V
V
VI
DC Input Voltage
VO
DC Output Voltage
Output in 3-STATE
V
Output in HIGH or LOW State (Note 3)
VI GND
IIK
IOK
IO
DC Input Diode Current
DC Output Diode Current
DC Output Current
mA
mA
50
VO GND
64
VO VCC Output at HIGH State
VO VCC Output at LOW State
mA
128
ICC
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
64
mA
mA
C
IGND
TSTG
128
65 to 150
Recommended Operating Conditions
Symbol
VCC
Parameter
Min
2.7
0
Max
3.6
5.5
32
Units
Supply Voltage
V
V
VI
Input Voltage
IOH
IOL
TA
HIGH-Level Output Current
LOW-Level Output Current
mA
mA
C
64
Free-Air Operating Temperature
40
0
85
t/ V
Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V
10
ns/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I Absolute Maximum Rating must be observed.
O
DC Electrical Characteristics
T
40 C to 85 C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
1.2
(Note 4)
V
V
V
V
Input Clamp Diode Voltage
Input HIGH Voltage
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
V
V
V
I
18 mA
0.1V or
IK
I
2.0
V
V
IH
O
Input LOW Voltage
0.8
V
0.1V
A
IL
O
CC
Output HIGH Voltage
V
0.2
I
I
I
I
I
I
I
I
100
OH
CC
OH
OH
OH
OL
OL
OL
OL
OL
2.4
V
8 mA
3.0
2.0
32 mA
V
Output LOW Voltage
2.7
0.2
0.5
100 A
OL
2.7
24 mA
16 mA
32 mA
64 mA
0.8V
3.0
0.4
V
3.0
0.5
3.0
0.55
I
Bushold Input Minimum Drive
3.0
75
75
V
V
I(HOLD)
I
I
A
A
(Note 5)
2.0V
I
Bushold Input Over-Drive
Current to Change State
Input Current
3.0
500
(Note 6)
(Note 7)
I(OD)
(Note 5)
500
I
3.6
3.6
10
1
V
V
V
V
5.5V
0V or V
0V
I
I
I
I
I
Control Pins
Data Pins
Power Off Leakage Current
CC
A
5
3.6
0
1
V
CC
I
100
A
A
0V V or V
5.5V
OFF
I
O
I
Power Up/Down 3-STATE
Output Current
V
V
V
V
0.5V to 3.0V
PU/PD
O
I
0–1.5V
100
GND or V
0.5V
CC
I
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3.6
3.6
5
5
A
A
OZL
O
O
I
3.0V
OZH
3
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DC Electrical Characteristics (Continued)
T
40 C to 85 C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
(Note 4)
I
I
I
I
I
3-STATE Output Leakage Current
Power Supply Current
3.6
3.6
3.6
3.6
3.6
10
0.19
5
A
mA
mA
mA
mA
V
V
O
5.5V
OZH
CC
Outputs High
Outputs Low
CCH
CCL
CCZ
CCZ
Power Supply Current
Power Supply Current
0.19
0.19
Outputs Disabled
Power Supply Current
V
V
5.5V,
Outputs Disabled
One Input at V
CC
O
I
Increase in Power Supply Current
(Note 8)
3.6
0.2
mA
0.6V
CC
CC
Other Inputs at V or GND
CC
Note 4: All typical values are at V
3.3V, T
25 C.
CC
A
Note 5: Applies to bushold versions only (74LVTH574).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.
CC
Dynamic Switching Characteristics (Note 9)
V
T
25 C
Typ
Conditions
CC
A
Symbol
Parameter
Units
C
50 pF, R
500
(V)
3.3
3.3
Min
Max
L
L
V
V
Quiet Output Maximum Dynamic V
0.8
0.8
V
V
(Note 10)
(Note 10)
OLP
OLV
OL
Quiet Output Minimum Dynamic V
OL
Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
40 C to 85 C
50 pF, R 500
A
C
L
L
Symbol
Parameter
Units
V
3.3V 0.3V
V
2.7V
Max
CC
CC
Min
Typ
Max
Min
(Note 11)
f
t
t
t
t
t
t
t
t
t
t
t
Maximum Clock Frequency
Propagation Delay
150
1.8
1.8
1.5
1.5
2.0
2.0
2.0
0.3
3.3
150
1.8
1.8
1.5
1.5
2.0
2.0
2.4
0.0
3.3
MHz
ns
MAX
4.6
4.5
5.2
4.8
4.4
4.8
5.3
5.3
6.1
5.9
4.4
5.1
PHL
PLH
PZL
PZH
PLZ
PHZ
S
CP to O
n
Output Enable Time
Output Disable Time
ns
ns
Setup Time
ns
ns
ns
Hold Time
H
Pulse Width
W
Output to Output Skew (Note 12)
1.0
1.0
1.0
1.0
OSHL
OSLH
ns
Note 11: All typical values are at V
3.3V, T
25 C.
CC
A
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (t
) or LOW to HIGH (t
).
OSLH
OSHL
Capacitance (Note 13)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
Typical
Units
pF
C
C
V
V
Open, V 0V or V
4
6
IN
OUT
CC
CC
I
CC
CC
3.0V, V
0V or V
pF
O
Note 13: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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