74LVX273SJX [FAIRCHILD]
D Flip-Flop, LV/LV-A/LVX/H Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20;
| 型号： | 74LVX273SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | D Flip-Flop, LV/LV-A/LVX/H Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1993
Revised March 1999
74LVX273
Low Voltage Octal D-Type Flip-Flop
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
Features
■ Input voltage translation from 5V to 3V
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
Ordering Code:
Order Number Package Number
Package Description
74LVX273M
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX273SJ
74LVX273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
Data Inputs
Master Reset
D0–D7
MR
CP
Clock Pulse Input
Data Outputs
Q0–Q7
© 1999 Fairchild Semiconductor Corporation
DS011614.prf
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Truth Table
Operating Mode
Inputs
CP
Outputs
Qn
MR
Dn
Reset (Clear)
Load ’1’
L
H
H
X
X
H
L
L
H
L
Load ’0’
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
2.0V to 3.6V
0V to 5.5V
−20 mA
Input Voltage (VI)
DC Input Voltage (VI)
−0.5V to 7V
Output Voltage (VO)
0V to VCC
DC Output Diode Current (IOK
)
Operating Temperature (TA)
−40°C to +85°C
0 ns/V to 100 ns/V
VO = −0.5V
−20 mA
+20 mA
Input Rise and Fall Time (∆t/∆V)
VO = VCC +0.5V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±25 mA
DC VCC or Ground Current
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
(ICC or IGND
)
±75 mA
−65°C to +150°C
180 mW
Storage Temperature (TSTG
Power Dissipation
)
DC Electrical Characteristics
T
= +25°C
T = −40°C to +85°C
A
A
V
Symbol
Parameter
Units
Conditions
CC
Min
1.5
2.0
2.4
Typ
Max
Min
1.5
2.0
2.4
Max
V
HIGH Level
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
IH
Input Voltage
V
V
V
V
LOW Level
0.5
0.8
0.8
0.5
0.8
0.8
IL
Input Voltage
V
V
HIGH Level
1.9
2.9
2.0
3.0
1.9
2.9
V
V
= V or V I
IL OH
= −50 µA
= −50 µA
= −4 mA
= 50 µA
= 50 µA
= 4 mA
OH
OL
IN
IH
Output Voltage
I
I
OH
OH
2.58
2.48
LOW Level
0.0
0.0
0.1
0.1
0.1
0.1
= V or V
I
IN
IH
IL OL
Output Voltage
V
I
I
OL
OL
0.36
±0.25
0.44
±2.5
I
3-STATE Output
µA
V
V
V
V
= V or V
IH IL
OZ
IN
Off-State Current
= V or GND
CC
OUT
I
I
Input Leakage Current
Quiescent Supply Current
3.6
3.6
±0.1
±1.0
µA
µA
= 5.5V or GND
IN
IN
IN
4.0
40.0
= V or GND
CC
CC
Noise Characteristics (Note 3)
T
= 25°C
V
(V)
A
CC
C
L
(pF)
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
Typ
Limit
V
V
V
V
3.3
3.3
3.3
3.3
0.5
0.8
−0.8
2.0
V
V
V
V
50
OLP
OLV
IHD
ILD
OL
Quiet Output Minimum Dynamic V
−0.5
50
50
50
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
0.8
Note 3: Input t = t = 3ns
r
f
3
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AC Electrical Characteristics
T
= +25°C
T = −40°C to +85°C
A
V
(V)
A
CC
C
(pF)
Symbol
Parameter
Units
L
Min
Typ
9.0
Max
16.9
20.0
11.0
14.5
17.8
21.1
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
20.5
24.0
13.0
16.5
20.5
24.0
t
t
Propagation
Delay Time
CP to Q
2.7
15
PLH
PHL
11.5
7.1
50
15
50
15
50
ns
3.3 ± 0.3
n
9.6
t
Propagation Delay
MR to Q
2.7
9.3
PHL
11.8
n
ns
3.3 ± 0.3
7.3
9.8
11.5
15.0
1.0
1.0
9.5
6.5
1.0
1.0
4.0
2.5
13.5
17.0
15
50
t
t
t
Setup Time
to CP
2.7
3.3 ± 0.3
2.7
8.0
5.5
1.0
1.0
4.0
2.5
S
ns
ns
ns
ns
ns
D
n
Hold Time
to CP
H
D
3.3 ± 0.3
2.7
n
Removal Time
REC
3.3 ± 0.3
MR to CP
Clock Pulse
Width
t
t
2.7
3.3 ± 0.3
2.7
8.0
5.5
7.5
9.5
6.5
8.5
W
W
MR Pulse
Width
3.3 ± 0.3
5.0
55
45
95
60
6.0
45
40
80
50
f
Maximum
Clock
2.7
110
60
15
50
15
50
50
MAX
MHz
ns
Frequency
3.3 ± 0.3
150
90
t
t
Output to Output
Skew (Note 4)
2.7
3.3
1.5
1.5
1.5
1.5
OSLH
OSHL
Note 4: Parameter guaranteed by design. t
= |t
− t
|, t
= |t
− t
|
PHLn
OSLH
PLHm
PLHn OSHL
PHLm
Capacitance
T
= +25°C
T = −40°C to +85°C
A
A
Symbol
Parameter
Units
Min
Typ
4
Max
10
Min
Max
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
10
pF
pF
pF
IN
C
C
6
OUT
PD
31
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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