74LVXC3245WM_09 [FAIRCHILD]
8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs; 8位双电源配置电压接口收发器与3态输出
| 型号： | 74LVXC3245WM_09 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2009
74LVXC3245
8-Bit Dual Supply Configurable Voltage Interface
Transceiver with 3-STATE Outputs
Features
■ Bidirectional interface between 3V and 3V-to-5V buses
■ Control inputs compatible with TTL level
■ Outputs source/sink up to 24 mA
General Description
The LVXC3245 is a 24-pin dual-supply, 8-bit configurable
voltage interface transceiver suited for PCMCIA and other
real time configurable I/O applications. The VCCA pin
accepts a 3V supply level. The A Port is a dedicated 3V
port. The VCCB pin accepts a 3V-to-5V supply level. The B
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Port is configured to track the VCCB supply level respec-
tively. A 5V level on the VCC pin will configure the I/O pins
at a 5V level and a 3V VCC will configure the I/O pins at a
■ Implements proprietary EMI reduction circuitry
■ Flexible VCCB operating range
■ Allows B Port and VCCB to float simultaneously when OE
is HIGH
3V level. The A Port should interface with a 3V host system
and the B Port to the card slots. This device will allow the
V
CCB voltage source pin and I/O pins on the B Port to float
■ Functionally compatible with the 74 series 245
when OE is HIGH. This feature is necessary to buffer data
to and from a PCMCIA socket that permits PCMCIA cards
to be inserted and removed during normal operation.
Ordering Code:
Order Number Package Number
Package Description
74LVXC3245WM
74LVXC3245QSC
74LVXC3245MTC
M24B
MQA24
MTC24
224-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol/s
Connection Diagram/s
Pin Descriptions
Pin Names
Description
Output Enable Input
Transmit/Receive Input
OE
T/R
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1994 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Truth Table/s
Inputs
Outputs
OE
L
T/R
L
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
L
H
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram/s
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCCA, VCCB
)
−0.5V to +7.0V
DC Input Voltage (VI) @ OE, T/R
−0.5V to VCCA +0.5V
Supply Voltage
DC Input/Output Voltage (VI/O
)
VCCA
2.7V to 3.6V
3.0V to 5.5V
0V to VCCA
@ An
@ Bn
−0.5V to VCCA +0.5V
−0.5V to VCCB +0.5V
VCCB
Input Voltage (VI) @ OE, T/R
DC Input Diode Current (IIK
@ OE, T/R
)
Input Output Voltage (VI/O)
±20 mA
±50 mA
±50 mA
@ An
@ Bn
0V to VCCA
0V to VCCB
−40°C to +85°C
8 ns/V
DC Output Diode (IOK) Current
DC Output Source or Sink Current (IO)
DC VCC or Ground Current
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (Δt/ΔV)
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
per Output Pin (ICC or IGND
and Max Current
)
±50 mA
±200 mA
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range (TSTG
)
−65°C to +150°C
±300 mA
DC Latch-Up Source or Sink Current
Note 2: The A Port unused pins (inputs or I/Os) must be held HIGH or
LOW. They may not float.
DC Electrical Characteristics
V
V
T
= 25°C
T = −40°C to +85°C
A
CCA
CCB
A
Symbol
Parameter
Units
Conditions
(V)
2.7
3.0
3.6
2.7
3.0
3.6
2.7
3.0
3.6
2.7
3.0
3.6
3.0
3.0
3.0
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.0
2.7
2.7
3.0
3.0
3.0
3.6
3.6
(V)
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.6
5.5
3.0
3.0
3.0
3.0
4.5
3.0
3.0
3.0
4.5
3.0
3.0
3.0
4.5
3.0
3.0
4.5
3.6
5.5
Typ
Guaranteed Limits
V
Minimum HIGH
Level Input
Voltage
A ,
2.0
2.0
2.0
2.0
2.0
2.0
V ≤ 0.1V
OUT
IHA
IHB
ILA
n
OE
2.0
2.0
2.0
2.0
or
≥V − 0.1V
T/R
CC
V
V
V
V
V
B
n
3.85
0.8
3.85
0.8
Maximum LOW
Level Input
Voltage
A ,
n
V
≤ 0.1V
OUT
OE
0.8
0.8
or
≥V − 0.1V
T/R
0.8
0.8
CC
V
V
B
0.8
0.8
ILB
n
0.8
0.8
1.65
2.9
1.65
2.9
Minimum HIGH Level
Output Voltage
2.99
2.85
2.65
2.5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= −100 μA
OUT
OHA
2.56
2.35
2.3
2.46
2.25
2.2
= −12 mA
OH
OH
OH
OH
= −24 mA
= −12 mA
= −24 mA
= −100 μA
2.3
2.1
2.0
V
V
2.99
2.85
2.65
4.25
0.002
0.21
0.11
0.22
0.002
0.21
0.18
2.9
2.9
OHB
OLA
OLB
OUT
2.56
2.35
3.86
0.1
2.46
2.25
3.76
0.1
= −12 mA
OH
OH
OH
V
V
= −24 mA
= −24 mA
= 100 μA
Maximum LOW Level
Output Voltage
OUT
0.36
0.36
0.42
0.1
0.44
0.44
0.5
= 24 mA
OL
OL
OL
= 12 mA
= 24 mA
= 100 μA
V
0.1
OUT
0.36
0.36
±0.1
±0.1
0.44
0.44
±1.0
±1.0
V
= 24 mA
OL
OL
= 24 mA
, GND
I
Maximum Input
Leakage Current @
OE, T/R
V = V
CCA
IN
I
μA
3
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DC Electrical Characteristics (Continued)
VCCA
VCCB
T
A = 25°C
T
A = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
3.6
3.6
(V)
3.6
5.5
Typ
Guaranteed Limits
IOZA
Maximum 3-STATE
Output Leakage
@ An
±0.5
±0.5
±5.0
±5.0
VI = VIL, VIH
OE = VCCA
O = VCCA, GND
,
µA
V
IOZB
Maximum 3-STATE
Output Leakage
@ Bn
3.6
3.6
3.6
5.5
±0.5
±0.5
±5.0
±5.0
VI = VIL, VIH
OE = VCCA
,
µA
mA
µA
V
O = VCCB, GND
∆ICC
Maximum
Bn
All Inputs
3.6
3.6
5.5
3.6
1.0
1.35
0.35
1.5
0.5
VI = VCCB–2.1V
VI = VCC–0.6V
ICC/Input
ICCA1
Quiescent VCCA
Supply Current
as B Port Floats
A
B
n = VCCA or GND
3.6
Open
5
50
n = Open, OE = VCCA,
T/R = VCCA, VCCB
=
Open
ICCA2
Quiescent VCCA
Supply Current
3.6
3.6
3.6
5.5
5
5
50
50
A
B
n = VCCA or GND,
n = VCCB or GND,
µA
µA
OE = GND, T/R = GND
ICCB
Quiescent VCCB
Supply Current
3.6
3.6
3.6
5.5
5
8
50
80
A
B
n = VCCA or GND,
n = VCCB or GND,
OE = GND, T/R = VCCA
VOLPA
VOLPB
VOLVA
VOLVB
VIHDA
VIHDB
VILDA
VILDB
Quiet Output
Maximum Dynamic
VOL
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
0.8
0.8
(Note 3)(Note 4)
V
V
V
V
V
V
V
V
0.8
(Note 3)(Note 4)
(Note 3)(Note 4)
(Note 3)(Note 4)
(Note 3)(Note 5)
(Note 3)(Note 5)
(Note 3)(Note 5)
(Note 3)(Note 5)
1.5
Quiet Output
Minimum Dynamic
VOL
−0.8
−0.8
−0.8
−1.2
2.0
Minimum HIGH
Level Dynamic
Input Voltage
2.0
2.0
3.5
Maximum LOW
Level Dynamic
Input Voltage
0.8
0.8
0.8
1.5
Note 3: Worst case package.
Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
Note 5: Max number of Data Inputs (n) switching. (n–1) inputs switching 0V to VCC level. Input-under-test switching:
VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.
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4
AC Electrical Characteristics
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
T
A = +25°C
T
A = −40°C to +85°C
C
L = 50 pF
C
C
L = 50 pF
CL = 50 pF
V
V
CCA = 2.7V–3.6V
CCB = 4.5V–5.5V
V
CCA = 2.7V–3.6V
CCB = 4.5V–5.5V
V
CCA = 2.7V–3.6V
CCB = 3.0V–3.6V
V
V
CCA = 2.7V–3.6V
CCB = 3.0V–3.6V
Symbol
Parameter
Units
V
V
Min
Typ
(Note 6)
4.8
Max
Min
Max
Min
Typ
(Note 7)
5.5
Max
Min
Max
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPHZ
tPLZ
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
A to B
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.0
6.5
6.5
7.5
8.0
8.5
9.5
9.0
8.0
7.5
9.5
6.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.5
7.0
7.0
8.0
8.5
9.0
10.0
9.5
8.5
8.0
10.0
7.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
8.5
8.0
7.0
7.5
9.0
9.5
10.0
9.0
9.5
8.0
9.5
6.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.0
8.5
ns
ns
ns
ns
ns
ns
3.9
5.2
Propagation Delay
B to A
3.8
4.4
7.5
4.3
5.1
8.0
Output Enable Time
OE to B
4.7
6.0
9.5
4.8
6.1
10.0
10.5
9.5
Output Enable Time
OE to A
5.9
6.4
5.4
5.8
Output Disable Time
OE to B
4.0
6.3
10.0
8.5
3.8
4.5
Output Disable Time
OE to A
4.6
5.2
10.0
7.0
3.1
3.4
Output to Output
Skew (Note 8)
Data to Output
1.0
1.5
1.5
1.0
1.5
1.5
ns
Note 6: Typical values at VCCA = 3.3V, VCCB = 5.0V @ 25°C.
Note 7: Typical values at VCCA = 3.3V, VCCB = 3.3V @ 25°C.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
Parameter
Typ
4.5
10
Units
pF
Conditions
Input Capacitance
VCC = Open
VCCA = 3.3V
VCCB = 5.0V
VCCB = 5.0V
VCCA = 3.3V
CI/O
Input/Output Capacitance
pF
CPD
Power Dissipation
A→B
B→A
50
40
pF
pF
Capacitance (Note 9)
Note 9: CPD is measured at 10 MHz.
5
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Power Up Considerations
To insure the system does not experience unnecessary ICC
figured as inputs. With VCCA receiving power first, the A
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
•
A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
•
•
•
Power up the control side of the device first. This is the
CCA side.
V
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
OE should ramp with or ahead of VCCA. This will help
guard against bus contention.
The Transmit/Receive control pin (T/R) should ramp with
V
CCA, this will ensure that the A Port data pins are con-
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Floatable Pin
Allowed
VCCA
VCCB
Device Type
T/R
OE
A Side I/O
B Side I/O
3V
3V to 5.5V
ramp
ramp
logic
yes, VCCB and B
74LVXC3245
outputs
(power up 1st)
configurable
with VCCA
with VCCA
0V or VCCA
I/O’s w/ OE HIGH
Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
Configurable I/O Application for PCMCIA Cards
Block Diagram
The LVXC3245 is a 24-pin dual supply device well suited
for PCMCIA configurable I/O applications. Ideal for low
power notebook designs, the LVXC3245 consumes less
than 1 mW of quiescent power in all modes of operation.
The LVXC3245 meets all PCMCIA I/O voltage require-
ments at 5V and 3.3V operation. By tying VCCB of the
will always experience rail to rail output swings, maximizing
the reliability of the interface.
The VCCA pin on the LVXC3245 must always be tied to a
3V power supply. This voltage connection provides internal
references needed to account for variations in VCCB. When
connected as in the figure above, the LVXC3245 meets all
the voltage and current requirements of the ISA bus stan-
dard (IEEE P996).
LVXC3245 to the card voltage supply, the PCMCIA card
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA24
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
9
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