74LVXZ161284MEX [FAIRCHILD]
Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection; 低压IEEE 161284翻译收发器加电保护
| 型号： | 74LVXZ161284MEX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage IEEE 161284 Translating Transceiver with Power-Up Protection |
| 文件： | 总11页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2002
Revised May 2002
74LVXZ161284
Low Voltage IEEE 161284 Translating Transceiver
with Power-Up Protection
General Description
The LVXZ161284 contains eight bidirectional data buffers
Features
I Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
and eleven control/status buffers to implement
a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
I Translation capability allows outputs on the cable side to
interface with 5V signals
I All inputs have hysteresis to provide noise margin
I B and Y output resistance optimized to drive external
cable
Outputs on the cable side can be configured to be either
open drain or high drive ( 14 mA) and are connected to a
separate power supply pin (VCC-Cable) that allows these
I B and Y outputs in high impedance mode during power
down
outputs to be driven by a higher supply voltage than
the A-side. The pull-up and pull-down series termination
resistance of these outputs on the cable side is optimized
to drive an external cable. In addition, the C inputs and the
B and Y outputs on the cable side contain internal pull-up
resistors connected to the VCC-Cable supply to provide
I C inputs and B, Y outputs on cable side have internal 1.4
kΩ pull-up resistors
I Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
I Replaces the function of two (2) 74ACT1284 devices
proper input termination and pull-ups for open drain output
mode.
I Power-up protection prevents errors when the printer is
powered on but no valid signal is at the input pins
(A9 - A13).
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
This device also has an added power-up protection feature
which forces the Y outputs (Y9 - Y13) to a high state after
power-on until one of the associated inputs (A9 - A13) goes
HIGH. When an associated input (A9 - A13) goes HIGH, all
Y outputs (Y9 - Y13) are activated.
Ordering Code
Package
Order Number
Package Description
Number
74LVXZ161284MEA
74LVXZ161284MEX
74LVXZ161284MTD
74LVXZ161284MTX
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
© 2002 Fairchild Semiconductor Corporation
DS500729
www.fairchildsemi.com
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
HD
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
DIR
A1–A8
B1–B8
A9–A13
Y9–Y13
Inputs or Outputs
Inputs
Outputs
A
14–A17
Outputs
C14–C17
PLHIN
PLH
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
HLHIN
HLH
Truth Table
Inputs
Outputs
DIR
HD
L
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13 (Note 1)
C14–C17 Data to A14–A17
PLH Open Drain Mode
L
H
L
B1–B8 Data to A1–A8, and
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
A1–A8 Data to B1–B8 (Note 2)
A9–A13 Data to Y9–Y13 (Note 1)
H
C
14–C17 Data to A14–A17
PLH Open Drain Mode
A1–A8 Data to B1–B8
A9–A13 Data to Y9–Y13
C14–C17 Data to A14–A17
H
H
Note 1: Y9–Y13 Open Drain Outputs with 1.4 kΩ pullups
Note 2: B1–B8 Open Drain Outputs with 1.4 kΩ pullups
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2
Logic Diagrams
Input Detection Circuit
FIGURE 1. Input Detection Circuit Timing
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage
VCC
−0.5V to +4.6V
Supply Voltage
VCC—Cable
−0.5V to +7.0V
VCC
3.0V to 3.6V
3.0V to 5.5V
0V to VCC
VCC—Cable Must Be ≥ VCC
Input Voltage (VI)—(Note 4)
A1–A13, PLHIN, DIR, HD
B1–B8, C14–C17, HLHIN
B1–B8, C14–C17, HLHIN
VCC—Cable
DC Input Voltage (VI)
Open Drain Voltage (VO)
Operating Temperature (TA)
−0.5V to VCC + 0.5V
−0.5V to +5.5V (DC)
−2.0V to +7.0V*
0V to 5.5V
−40°C to +85°C
*40 ns Transient
Output Voltage (VO)
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
B1–B8, Y9–Y13, PLH
−0.5V to VCC +0.5V
−0.5V to +5.5V (DC)
−2.0V to +7.0V*
*40 ns Transient
DC Output Current (IO)
A1–A8, HLH
25 mA
50 mA
84 mA
−50 mA
B1–B8, Y9–Y13
PLH (Output LOW)
PLH (Output HIGH)
Input Diode Current (IIK)—(Note 4)
DIR, HD, A9–A13, PLH, HLH, C14–C17
−20 mA
Output Diode Current (IOK
A1–A8, A14–A17, HLH
B1–B8, Y9–Y13, PLH
)
50 mA
−50 mA
DC Continuous VCC or Ground
Current
200 mA
Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Fairchild does not recom-
mend operation outside the databook specifications.
Storage Temperature
ESD
−65°C to +150°C
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
Human Body Model
Machine Model
Charged Device Model
4000V
200V
2000V
DC Electrical Characteristics
TA = 0°C
to +70°C
TA = −40°C
to +85°C
VCC
(V)
VCC—Cable
(V)
Symbol
Parameter
Units
Conditions
Guaranteed Limits
VIK
Input Clamp
Diode Voltage
Minimum
3.0
3.0
−1.2
−1.2
V
Ii = −18 mA
VIH
An, Bn, PLHIN, DIR, HD
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.0–3.6
3.3
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
3.0–5.5
5.0
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
2.0
2.3
2.6
0.8
0.8
1.6
0.4
0.8
0.2
2.8
2.4
2.0
2.23
3.1
HIGH Level
Input Voltage
Maximum
Cn
V
V
V
HLHIN
VIL
An, Bn, PLHIN, DIR, HD
LOW Level
Input Voltage
Minimum Input
Hysteresis
Cn
HLHIN
+
−
−
−
∆VT
VOH
An, Bn, PLHIN, DIR, HD
VT – VT
+
Cn
3.3
5.0
VT – VT
+
HLHIN
An, HLH
3.3
5.0
VT – VT
Minimum HIGH
Level Output
Voltage
3.0
3.0
IOH = −50 µA
IOH = −4 mA
IOH = −14 mA
IOH = −14 mA
IOH = −500 µA
3.0
3.0
Bn, Yn
Bn, Yn
PLH
3.0
3.0
V
3.0
4.5
3.15
3.15
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4
DC Electrical Characteristics (Continued)
TA = 0°C
to +70°C
TA = −40°C
to +85°C
VCC
(V)
VCC—Cable
Symbol
Parameter
Units
Conditions
(V)
Guaranteed Limits
VOL
Maximum LOW
Level Output
Voltage
An, HLH
3.0
3.0
3.0
3.0
3.0
3.0
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
3.0
3.0
4.5
3.0
4.5
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
0.2
0.4
0.2
0.4
IOL = 50 µA
IOL = 4 mA
IOL = 14 mA
IOL = 14 mA
IOL = 84 mA
IOL = 84 mA
Bn, Yn
Bn, Yn
PLH
0.8
0.8
V
0.77
0.85
0.8
0.77
0.95
0.9
PLH
RD
RP
IIH
IIL
Maximum Output
Impedance
B1 - B8, Y9 -Y13
60
60
(Note 5)(Note 7)
(Note 5)(Note 7)
55
55
Ω
Minimum Output
Impedance
B
1 - B8, Y9 - Y13
30
30
35
35
Maximum Pull-Up
Resistance
B1 - B8, Y9 - Y13,
C14 - C17
1650
1650
1150
1150
1650
1650
1150
1150
Ω
Ω
Minimum Pull-Up
Resistance
B1 -B8, Y9 - Y13
C14 - C17
Maximum Input
Current in
A9 - A13, PLHIN,
3.6
3.6
1.0
1.0
VI = 3.6V
HD, DIR, HLHIN
C14 - C17
µA
HIGH State
3.6
3.6
3.6
5.5
50.0
100
50.0
100
VI = 3.6V
VI = 5.5V
C14 -C17
Maximum Input
Current in
A9 - A13, PLHIN,
3.6
3.6
−1.0
−1.0
µA VI = 0.0V
mA VI = 0.0V
HD, DIR, HLHIN
C14 - C17
C14 - C17
A1 - A8
LOW State
3.6
3.6
3.6
5.5
−3.5
−5.0
20
−3.5
−5.0
20
IOZH
Maximum Output
Disable Current
(HIGH)
3.6
3.6
VO = 3.6V
µA VO = 3.6V
VO = 5.5V
B1 - B8
3.6
3.6
50
50
B
1 - B8
3.6
5.5
100
−20
−3.5
−5.0
350
−5
100
−20
−3.5
−5.0
350
−5
IOZL
Maximum
A1 - A8
B1 - B8
B1 - B8
Y9 - Y13
B1 - B8
3.6
3.6
µA
Output Disable
Current (LOW)
Maximum Power-Up
Disable Current
3.6
3.6
VO = 0.0V
mA
3.6
5.5
IOZPU
IOZPD
IOFF
0 to 1.5
(Note 8)
0 to 1.5
(Note 8)
0 to 1.5
(Note 8)
0 to 1.5
(Note 8)
µA VO = 5.5V
mA VO = 0.0V
µA VO = 5.5V
mA VO = 0.0V
Maximum Power-Down Y9 - Y13
350
−5
350
−5
Disable Current
Power Down
B1 - B8
B1 - B8, Y9 - Y13
,
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
100
100
250
250
100
100
250
250
µA VO = 5.5V
µA VI = 5.5V
µA (Note 6)
µA (Note 6)
Output Leakage
Power Down
PLH
IOFF
C14–C17, HLHIN
Input Leakage
IOFF—ICC Power Down
Leakage to VCC
IOFF—ICC2 Power Down Leakage
to VCC—Cable
ICC
Maximum Supply
Current
3.6
3.6
3.6
5.5
45
70
45
70
mA VI = VCC or GND
mA VI = VCC or GND
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH).
Note 6: Power-down leakage to VCC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN
to 5.5V and measuring the resulting ICC or ICC—Cable
)
.
Note 7: This parameter is guaranteed but not tested, characterized only.
Note 8: Connect all VCC pins and VCC-Cable pins when forcing voltage applied, DIR = HD = 0V.
5
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AC Electrical Characteristics
TA = 0°C to +70°C
TA = −40°C to +85°C
VCC = 3.0V–3.6V
VCC = 3.0V–3.6V
Figure
Number
Symbol
Parameter
Units
VCC—Cable = 3.0V–5.5V
VCC—Cable = 3.0V–5.5V
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
10.0
40.0
40.0
40.0
40.0
15.0
15.0
50.0
50.0
50.0
50.0
25.0
25.0
25.0
25.0
10.0
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
44.0
44.0
44.0
44.0
44.0
44.0
44.0
44.0
12.0
44.0
44.0
44.0
44.0
18.0
18.0
50.0
50.0
50.0
50.0
28.0
28.0
28.0
28.0
12.0
tPHL
A1–A8 to B1–B8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 2
Figure 3
Figure 4
Figure 4
Figure 2
Figure 3
Figure 4
Figure 4
(Note 10)
Figure 2
Figure 3
Figure 4
Figure 4
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tSKEW
tPHL
tPLH
tPHL
tPLH
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tpEN
A1–A8 to B1–B8
B1–B8 to A1–A8
B1–B8 to A1–A8
A9–A13 to Y9–Y13
A9–A13 to Y9–Y13
C14–C17 to A14–A17
C14–C17 to A14–A17
LH-LH or HL-HL
PLHIN to PLH
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
PLHIN to PLH
HLHIN to HLH
HLHIN to HLH
Output Disable Time
DIR to A1–A8
ns
ns
ns
ns
Figure 8
Figure 9
Figure 10
Figure 3
Figure 3
Output Enable Time
DIR to A1–A8
Output Disable Time
DIR to B1–B8
Output Enable Time
HD to B1–B8, Y9–Y13
Output Disable Time
HD to B1–B8, Y9–Y13
tpDIS
ns
ns
tpEN–tpDIS Output Enable-
Output Disable
tSLEW
tPLH
tPHL
tr, tf
Output Slew Rate
B1–B8, Y9–Y13
0.05
0.05
0.40
0.40
120
120
0.05
0.05
0.40
0.40
120
120
V/ns
ns
Figure 6
Figure 5
Figure 7
(Note 11)
tRISE and tFALL
B1–B8 (Note 9),
Y9–Y13 (Note 9)
Note 9: Open Drain
Note 10: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A1–A8 to B1–B8, A9–A13 to Y9–Y13
(ii) B1–B8 to A1–A8
(iii) C14–C17 to A14–A17
Note 11: This parameter is guaranteed but not tested, characterized only.
Capacitance
Symbol
Parameter
Input Capacitance
CI/O (Note 12) I/O Pin Capacitance
Typ
3
Units
pF
Conditions
CIN
VCC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN
VCC = 3.3V
)
5
pF
Note 12: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012
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6
AC Loading and Waveforms
Pulse Generator for all pulses: Rate ≤1.0 MHz; ZO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns.
FIGURE 2. Port A to B and A to Y Propagation Delay Waveforms
FIGURE 3. Port A to B and A to Y Output Waveforms
FIGURE 4. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms
7
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AC Loading and Waveforms (Continued)
FIGURE 5. Port A to B and A to Y HL Slew Test Load and Waveforms
FIGURE 6. Port A to B and A to Y LH Slew Test Load and Waveforms
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8
AC Loading and Waveforms (Continued)
tr = Output Rise Time, Open Drain
tf = Output Fall Time, Open Drain
FIGURE 7. Ports A to B and A to Y Rise and Fall Test Load and Waveforms for Open Drain Outputs
FIGURE 8. tPHZ and tPLZ Test Load and Waveforms, DIR to A1–A8
9
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AC Loading and Waveforms (Continued)
FIGURE 9. tPZH and tPZL Test Load and Waveforms, DIR to A1–A8
FIGURE 10. tPHZ and tPLZ Test Load and Waveforms
DIR to B1–B8
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10
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
11
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