74OL6011300 [FAIRCHILD]
Logic IC Output Optocoupler, 1-Element, 5300V Isolation, 15MBps, PLASTIC, DIP-6;
| 型号： | 74OL6011300 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Logic IC Output Optocoupler, 1-Element, 5300V Isolation, 15MBps, PLASTIC, DIP-6 |
| 文件： | 总15页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2007
74OL6000, 74OL6001, 74OL6010, 74OL6011
Optoplanar® High-Speed Logic-to-Logic Optocouplers
tm
LSTTL to
TTL Buffer
TTL Inverter
CMOS Buffer
CMOS Inverter
Description
OPTOLOGIC™ is the first family of truly logic compatible
optically coupled logic interface gates.
74OL6000
74OL6001
74OL6010
74OL6011
The family consists of four device types offering LSTTL
to TTL and LSTTL to CMOS interfacing. Each of these
interfacing functions is available as a buffer (A = B), or
as an inverter (A = B).
Features
The LSTTL input compatibility is provided by an input
integrated circuit, with industry standard logic levels.
This input amplifier IC switches a temperature compen-
sated current source driving a high speed 850nm
AlGaAs LED emitter. This novel integration scheme
eliminates CTR degradation over time and temperature.
■ Industry first LSTTL to TTL and LSTTL to CMOS
complete logic-to-logic optocoupler
■ Incorporates LED drive circuitry — use as a logic gate
■ Very high speed
■ Choice of buffer or inverter
■ Choice of TTL or CMOS compatible output up to 15
The emitter is optically coupled to an integrated photode-
tectorꢁhigh-gain, high-speed output amplifier IC. The
superior 15ꢀVꢁ/S common-mode noise rejection is
ensured through the use of an optically transparent
noise shield.
volts
■ Fan-out of 10 TTL loads, fan-in 1 LSTTL load
■ Internal noise shield — very high CMR of 15ꢀVꢁ/S
■ UL recognized (File #E90700)
■ Same noise immunity as LSTTLꢁTTL.
The TTL compatible output has a totem-pole with a
fan-out of 10. The CMOS compatible output has an open
collector Schottꢀy-clamped transistor that interfaces to
any CMOS logic between 4.5 and 15 volts. The
74OL6010ꢁ11 may also by used to drive power MOSFETs
or transistors up to 15 volts.
Applications
■ Transmission line interface — receiver and driver
■ Excellent as bridged receiver in fast LAN highways
■ Bus interface
The Optologic coupler family typically offers propagation
of delays of 60 ns and can support 15 MBaud data
communication.
■ Logic family interface with ground loop noise
elimination
■ High speed ACꢁDC voltage sensing
■ Driver for power semiconductor devices
■ Level shifting
The two input chips and the output chip are assembled
in a 6-pin DIP high insulation voltage plastic pacꢀage.
®
Fairchild’s proprietary OPTOPLANAR construction pro-
■ Replaces fast pulse transformers
vides a withstand test voltage of 5300 VRMS (1 minute).
Package
Symbol
6
6
BUFFER
1
1
6
INVERTER
1
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
Circuit Diagrams
Vcc
Vcc
Vcc
RL
22 kΩ TYP.
150 Ω TYP.
INPUT
OUTPUT
GND
LSTTL INPUT CIRCUIT
OUTPUT
GND
CMOS OUTPUT CIRCUIT
GND
TTL OUTPUT CIRCUIT
All Inputs
74OL6000/01 Output
74OL6010/11 Output
Pin Configuration
1
6
5
4
(Input VCC) VCCI
(Data In) VIN
VCCO (Output VCC)
2
3
VO (Data Out)
(Input Ground) GND
GNDO (Output Ground)
Device Configuration
Logic Compatibility
Part Number
74OL6000
Input
LSTTL
LSTTL
LSTTL
LSTTL
Output
TTL
Logic Function
Buffer
Output Configuration
Totem Pole
Totem Pole
74OL6001
TTL
Inverter
74OL6010
CMOS
CMOS
Buffer
Open Collector
Open Collector
74OL6011
Inverter
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
2
Schematics
74OL6000
74OL6001
NOISE
NOISE
SHIELD
SHIELD
1
2
3
1
2
3
6
5
4
6
5
4
LSTLL to TTL Buffer
74OL6010
LSTLL to TTL Inverter
74OL6011
NOISE
NOISE
SHIELD
SHIELD
1
1
2
3
6
5
4
6
5
4
2
3
LSTLL to CMOS Buffer
LSTLL to CMOS Inverter
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
3
Absolute Maximum Ratings (T = 25°C unless otherwise specified)
A
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Device
Value
Units
TOTAL DEVICE
T
Storage Temperature
All
All
All
All
-55 to +125
0 to +70
°C
°C
STG
T
Operating Temperature
Lead Solder Temperature
Power Dissipation
OPR
T
260 for 10 sec
350
°C
SOL
P
mW
D
EMITTER
V
Input Supply Voltage
Input Voltage
All
All
7
7
V
V
CCI
V
IN
DETECTOR
I
Average Output Current
Output Supply Voltage
All
40
7
mA
V
O (avg)
V
74OL6000ꢁ01
74OL6010ꢁ11
74OL6000ꢁ01
74OL6010ꢁ11
CCO
18
7
V
Output Voltage
V
O
18
Electrical Characteristics (T = 0°C to 70°C unless otherwise specified)
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Units
Fig.
CM
Common Mode Transient
Immunity at Logic High Level
Output
V
V
= 5V, V
CCO
= 5V,
5000
15000
Vꢁ/S
Vꢁ/S
pF
16, 19
H
CCI
CM
= 50 Vp-p
= 5V, V
CCO
CM
Common Mode Transient
Immunity at Logic Low Level
Output
V
V
= 5V,
-5000 -15000
0.005
16, 19
L
CCI
CM
= 50 Vp-p
C
Common Mode Coupling
Capacitance
CM
(1)
C
Capacitance (input-output)
V
= 0, f = 1MHz
0.7
pF
I-O
I-O
V
Withstand Insulation Test
Voltage
T = 25°C, t = 1 min,
5300
VRMS
ISO
A
(1)
I
≤ 2mA
I-O
(1)
11
R
Insulation Resistance
V
= 500 VDC
10
Ω
ISO
I-O
Note:
1. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together.
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
4
Electrical Characteristics (T = 0°C to 70°C unless otherwise specified)
A
(2)
TTL Output 74OL6000, 74OL6001
Test Conditions
Symbol
Parameter
74OL6000 74OL6001
74OL6000/01
Min. Typ.* Max. Units
V
Input Supply Voltage
4.5
4.5
2.0
5.0
5.0
5.5
5.5
V
V
CCI
V
Output Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Voltage
CCO
V
V
IH
V
0.8
-1.2
40.0
V
IL
IK
IH
V
V
V
V
V
V
V
= 4.5V, I = -18mA
V
CCI
CCI
CCI
CCI
CCI
CCI
I
I
High-Level Input Current
Low-Level Input Current
Input Supply Current (HIGH)
Input Supply Current (LOW)
High-Level Output Voltage
= 5.5V, V = 4.5V
1.0
/A
/A
mA
mA
V
IH
I
= 5.5V, V = 0.4V
-200.0 -400.0
IL
IL
I
= 5.5V, V = V
10.0
10.0
3.0
14.0
14.0
CCIH
IN
IH
IL
I
= 5.5V, V = V
IN
CCIL
V
V
V
= 2.0V
= 0.8V
V
V
= 0.8V
= 2.0V
= 4.5V, V
= -400/A
= 4.5V,
= 4.5V,
= 4.5V,
= 4.5V,
2.4
OH
IN
IN
IN
IN
CCO
CCO
CCO
CCO
CCO
CCO
I
OH
V
Low-Level Output Voltage
V
= 4.5V, V
CCI
= 16mA
0.3
0.6
0.5
V
OL
I
OL
V
= 4.5V, V
= 4mA
CCI
I
OL
I
High-Level Output Current
Low-Level Output Current
Short-Circuit Output Current
V
V
= V
V
V
= V
V
V
= 4.5V, V
= 2.4V
-8.0
-10.0
mA
mA
OH
IN
IN
IH
IN
IN
IL
CCI
OH
I
= 0.8 V
= 2.0V
V
V
= 4.5V, V
= 0.6V
= 4.5V, 16.0
OL
CCI
OL
I
V
V
= V
= V
V
V
= V
= V
V
= 5.5V, V
= 5.5V, -5.0
-25.0
9.0
-40.0
15.0
mA
mA
OS
IN
IN
IH
IH
IN
IN
IL
IL
CCI
I
Output Supply Current
(HIGH)
V
V
= 5.5V, V = V
,
CCOH
CCI
O
OH
= 5.5V
CCO
I
Output Supply Current
(LOW)
V
= V
V
= V
V
V
= 5.5V, V = V ,
OL
8.0
12.0
mA
CCOL
IN
IL
IN
IH
CCI
O
= 5.5V
CCO
*All typical values are at T =25°C
A
Switching Characteristics (T = 25°C unless otherwise specified)
A
(2)
TTL Output 74OL6000, 74OL6001
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units Fig.
t
Propagation Delay Time For Output Low
Level
V
= 5V, V = 5V
CCO
60
100
ns
15, 17
PHL
CCI
t
Propagation Delay Time For Output High
Level
70
100
ns
15, 17
PLH
t
Output Rise Time For Output High Level
Output Fall Time For Output Low Level
45
5
ns
ns
15, 17
15, 17
r
t
f
Note:
2. The V
and V
supply voltages to the device must each be bypassed by a 0.1/F capacitor or larger. This can
CCO
CCI
be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize
the operation of the high-gain amplifiers. Failure to provide the bypass will impair the DC and switching properties.
The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20.
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
5
Electrical Characteristics (T = 0°C to 70°C Unless otherwise specified)
A
(3)
CMOS Output 74OL6010 and 74OL6011
Test Conditions
Symbol
Parameter
Input Supply Voltage
Output Supply Voltage
74OL6010 74OL6011
74OL6010/11
Min. Typ.*
Max. Units
V
4.5
4.5
2.0
5.0
5.5
V
V
CCI
(4)
V
15.0
CCO
V
High-Level Input Voltage
Low-Level Input Voltage
Input Clamp Voltage
V
IH
V
0.8
-1.2
V
IL
IK
IH
V
V
V
V
V
V
V
= 4.5V, I = -18mA
V
CCI
CCI
CCI
CCI
CCI
CCI
I
I
High-Level Input Current
Low-Level Input Current
Input Supply Current (HIGH)
Input Supply Current (LOW)
Low-Level Output Voltage
= 5.5V, V = 4.5V
1.0
-200.0
10.0
10.0
0.4
40.0
-400.0
14.0
14.0
0.6
/A
/A
mA
mA
V
IH
I
= 5.5V, V = -0.4V
IL
IL
I
= 5.5V, V = V
IN
CCIH
IH
IL
I
= 5.5V, V = V
IN
CCIL
V
V
= 0.8V
V
= 2.0V
= 4.5V, V
= 4.5V,
OL
IN
IN
CCO
I
= 16mA
OL
V
= 4.5V, V
= 4.5V,
0.5
CCI
CCO
I
= 4mA
OL
I
High-Level Output Current
Low-Level Output Current
V
V
V
= V
V
V
V
= V
V
V
= 4.5V, V = 15V,
1.0
100.0
/A
mA
mA
OH
IN
IN
IN
IH
IN
IN
IN
IL
CCI
OH
= 4.5–15V
CCO
I
= 0.8V
= 2.0V
V
V
= 4.5V, V = 0.6V,
16.0
OL
CCI
OL
= 4.5–15V
CCO
I
Output Supply Current
(HIGH)
= V
= V
V
V
= 5.5V, V = V ,
OH
9.0
11.0
8.0
12.0
18.0
12.0
18.0
CCOH
IH
IL
IL
CCI
O
= 4.5V
CCO
V
V
= 5.5V, V = V
,
CCI
O
OL
OL
OL
= 15V
CCO
I
Output Supply Current
(LOW)
V
= V
V
= V
V
V
= 5.5V, V = V
,
mA
CCOL
IN
IN
IH
CCI
O
= 4.5V
CCO
V
V
= 5.5V, V = V
,
11.0
CCI
O
= 15V
CCO
*All typical values are at T =25°C
A
Switching Characteristics (T = 25°C Unless otherwise specified)
A
(3)
TTL Output 74OL6010 and 74OL6011
Symbol
Parameter
Test Conditions
= 5V, V = 5V,
R = 470Ω
Min. Typ. Max.
Units
Fig.
t
Propagation Delay Time For Output
Low Level
V
60
100
50
5
120
ns
ns
ns
ns
15, 18
15, 18
15, 18
15, 18
PHL
PLH
CCI
CCO
L
t
Propagation Delay Time For Output
High Level
180
t
Output Rise Time For Output High
Level
r
t
Output Fail Time For Output Low Level
f
Notes:
3. The V
and V
supply voltages to the device must each be bypassed by a 0.1/F capacitor or larger. This can
CCO
CCI
be either a ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize
the operation of the high-gain amplifiers. Failure to provide the bypass will impair the DC and switching properties.
The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20.
4. For example, assuming a V
of 5.0V, and an ambient temperature of 70°C, the maximum allowable V
is 12.1V.
CCI
CCO
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
6
Typical Performance Curves
Figure 1. Input Current vs. Ambient Temperature
Figure 2. Input Supply Current vs. Ambient Temperature
15
100
14
13
IIH
0
12
ICCIH - 74OL6000/10
ICCIL - 74OL6001/11
11
VCCI = 5.5V
VIH = 4.5V
VIL = 0.4V
-100
-200
-300
10
9
IIL
8
ICCIH - 74OL6001/11
ICCIL - 74OL6000/10
7
6
VCCI = 5.5V
5
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
Figure 3. Output Supply Current vs. Ambient Temperature
Figure 4. Output Current vs. Ambient Temperature
60
15
50
IOL
12
40
VCCI = 4.5V
VCCO = 4.5V
30
ICCOH
9
VOL = 0.6V
VOH = 2.4V
ICCOL
ICCOH
ICCOL
20
10
0
6
ICCOH
ICCOL
74OL6010/11
VCCI = 5.5V
VCCO = 15V
74OL6010/11
VCCI = 5.5V
VCCO = 5.5V
IOH
-10
-20
-30
3
0
74OL6000/01
74OL6000/01
VCCI = 5.5V
VCCO = 5.5V
-40
-20
0
20
40
60
80 100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
Figure 5. High-Level Output Voltage vs. Ambient Temperature
Figure 6. Low-Level Output Voltage vs. Ambient Temperature
0.5
5
VCCI = 4.5V
V
CCO = 4.5V
4
3
2
IOH = -400µA
0.4
@ IOL
= 16mA
= 4mA
0.3
0.2
0.1
@ IOL
1
0
V
V
CCI
= 4.5V
CCO = 4.5V
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
7
Typical Performance Curves (Continued)
Figure 7. 74OL6010/11 Leakage Current vs.
Figure 8. 74OL6000/01 Switching Times vs.
Ambient Temperature
Ambient Temperature
5
VCCI = 5.0V
V
CCO = 5.0V
VCCIN = 4.5V
VCCO = 15V
VOUT = 15V
P.W = 200ns
PERIOD = 1µS
4
3
2
1
200
100
50
tPLH
tPHL
tr
10
5
tf
0
-40
1
-40
-20
0
20
40
60
80
100
-20
0
20
40
60
80 100
TA - AMBIENT TEMPERATURE (˚C)
TA - AMBIENT TEMPERATURE (˚C)
Figure 9. 74OL6010/11 Switching Times vs.
Ambient Temperature
Figure 10. Common Mode Rejection vs.
Common Mode Voltage
11
10
9
VCCO = 5V
CCO = 15V
VCCI = 5V
RL = 470Ω
P.W = 200ns
PERIOD = 1µS
V
tPLH
tPLH
tr
tPHL
tr
200
100
50
8
7
VCCO = 5V
VCCO = 5V
VOH = 2V
VOL = 0.8V
6
5
RL = 470Ω (74OL6010/6011)
4
3
10
5
tf
tf
2
1
1
-40
-20
0
20
40
60
80 100
0
500
1000
15000
2000
2500
TA - AMBIENT TEMPERATURE (˚C)
VCM - COMMON MODE TRANSIENT
Figure 11. Supply Current vs. Supply Voltage
Figure 12. Power Dissipation vs. Ambient Temperature
12
MAXIMUM ALLOWABLE POWER
DISSIPATION @ TA = 25˚C
ICCO
ICC
10
8
300
200
100
0
@TA = 55°C
6
VCCO
RANGE FOR 74OL6000/6001
V
CCI = 5.5V
@T
@T
A
A
= 70°C
= 85°C
4
2
V
CCI = 4.5V
0
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
VCCO - OUTPUT SUPPLY VOLTAGE (V)
V
CC - SUPPLY VOLTAGE (V)
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
8
Typical Performance Curves (Continued)
Figure 14. Input Current vs. Input Voltage
Figure 13. Input Threshold Voltage vs. Ambient Temperature
1.6
100
0
1.5
1.4
1.3
1.2
-100
-200
-300
1.1
VCCI = 5.0V
VCCO = 5.0V
1.0
VCCI = 4.5V
0.0
-40
0
1
2
3
4
5
6
-20
0
20
40
60
80
100
T
A - AMBIENT TEMPERATURE (°C)
VIN - INPUT VOLTAGE (V)
Test Circuits
Figure 15. Switching Time Test Circuit
VCCI
+5 V
VCCO
+5 V
1
2
3
6
5
4
.1µF
.1µF
470Ω (74OL6010/11)
PULSE
GEN
PW =200ns
PERIOD = 1
tr = 5ns
Zo = 50Ω
µS
VO
CL*
*CL = 15pF STRAY CAPACITANCE
INCLUDING PROBE
Figure 16. Common Mode Rejection Test Circuit
VCCO
+5 V
1
2
3
6
5
6
.1µF
1kΩ
.1µF
470Ω (74OL6010/11)
H/L
L/H
+
-
V
CM
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
9
Switching and Rejection Waveforms
Figure 18. Switching Parameters 74OL6010/11
Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature
INPUT, VI
3.2V
INPUT, VI 3.2V
1.3V
1.3V
tPHL
tPLH
tPHL
tPLH
90%
50%
10%
90%
1.3V
OUTPUT, VO
(74OL6000)
OUTPUT, VO
(74OL6010)
10%
tr
tf
tf
tr
tr
tf
tf
tr
90%
50%
90%
OUTPUT, VO
(74OL6011)
OUTPUT, VO
(74OL6001)
1.3V
10%
10%
tPHL
tPLH
tPHL
tPLH
Figure 19. Common Mode Rejection Waveforms
50V
dVCM
dt
VCM
tr
VCM
0V
=
VOH
CMH
VO = 2.0V (MIN.)
VO = 0.8V (MAX.)
VOL
CML
PCB Layout
Figure 20. Suggested PCB Layout
INPUT
V
CC
BUS
INPUT
GND
BUS
OUTPUT
GND
BUS
OUTPUT
V
CC
BUS
1
2
6
5
DATA
IN
DATA
OUT
.1µF
.1µF
3
4
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
10
Package Dimensions
Through Hole
Surface Mount
0.350 (8.89)
0.330 (8.38)
PIN 1
ID.
PIN 1
ID.
3
1
0.270 (6.86)
0.240 (6.10)
0.270 (6.86)
0.240 (6.10)
6
0.350 (8.89)
0.330 (8.38)
0.300 (7.62)
TYP
0.070 (1.78)
0.045 (1.14)
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
0.165 (4.18)
0.016 (0.41)
0.008 (0.20)
0.200 (5.08)
0.115 (2.92)
0.020 (0.51)
MIN
0.016 (0.40) MIN
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.315 (8.00)
MIN
0.154 (3.90)
0.100 (2.54)
0.405 (10.30)
MAX
0.016 (0.40)
0.008 (0.20)
Lead Coplanarity : 0.004 (0.10) MAX
0.300 (7.62)
TYP
0.022 (0.56)
0.016 (0.41)
0° to 15°
0.100 (2.54)
TYP
Recommended Pad Layout for
Surface Mount Leadform
0.4” Lead Spacing
0.070 (1.78)
PIN 1
ID.
0.060 (1.52)
0.270 (6.86)
0.240 (6.10)
0.415 (10.54)
0.100 (2.54)
0.295 (7.49)
0.350 (8.89)
0.330 (8.38)
0.030 (0.76)
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
0.135 (3.43)
0.154 (3.90)
0.100 (2.54)
0.016 (0.40)
0.008 (0.20)
0.004 (0.10)
MIN
0° to 15°
0.022 (0.56)
0.016 (0.41)
0.400 (10.16)
TYP
0.100 (2.54) TYP
Note:
All dimensions are in inches (millimeters).
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
11
Ordering Information
Option
S
Order Entry Identifier
Description
.S
.SD
Surface Mount Lead Bend
SD
Surface Mount; Tape and Reel
0.4" Lead Spacing
W
.W
300
300W
3S
.300
.300W
.3S
VDE 0884
VDE 0884, 0.4" Lead Spacing
VDE 0884, Surface Mount
VDE 0884, Surface Mount, Tape and Reel
3SD
.3SD
Marking Information
1
2
74OL6000
6
V XX YY K
5
3
4
Definitions
1
2
3
Fairchild logo
Device number
VDE marꢀ (Note: Only appears on parts ordered with VDE
option – See order entry table)
4
5
6
Two digit year code, e.g., ‘03’
Two digit worꢀ weeꢀ ranging from ‘01’ to ‘53’
Assembly pacꢀage code
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
12
Reflow Profile
300
250
200
150
100
50
215°C, 10–30 s
225 C peak
Time above 183°C, 60–150 sec
Ramp up = 3C/sec
• Peak reflow temperature: 225°C (package surface temperature)
• Time of temperature higher than 183°C for 60–150 seconds
• One time soldering reflow is recommended
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (Minute)
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
13
Application
Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates
in the design.
The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line
receivers. The system show above illustrates an optically isolated transmitter and multidrop receiver system. The net-
worꢀ uses a 74OL6000 and buffer (Figure D) to isolate the transmitter and drive the 75Ω coax cable. This application
uses a 1000 ft. aerial suspension 75Ω CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as
bridged receivers, and as many as 30 receivers could be placed along the line with minimal signal degradation. The
communication cable is terminated with a single 75Ω load at the far end of the line.
Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS).
Traces 1-3 in Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic
bridged terminations. Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The
data quality is well preserved in that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmit-
ter.
The data communication system is completely optically isolated from all of the terminal equipments. Power for the
transmitter (V
senger wire.
) and receiver (V ) is taꢀen from an isolated power supply and distributed through a drain or mes-
CCO
CCI
Figure A
Figure B
Figure C
HORIZONTAL = 20ns/DIV 42-11
VERTICAL = 2V/DIV
HORIZONTAL = 20ns/DIV 42-12, 02
VERTICAL = 2V/DIV
HORIZONTAL = 20ns/DIV 42-13/03
VERTICAL = 2V/DIV
1000 FT.
3
1
2
0.1 µ
F
75
Ω
10 Ω
TERMINAION
250 FT.
250 FT.
250 FT.
250 FT.
BUFFER
74
6000
OL
2N4252
100 µ
F
74
6001
74
6001
OL
74
6001
OL
74
6001
OL
OL
4
8
5
9
6
7
1.1 KΩ
LS04
LS04
LS04
LS04
10
11
2N2222
ALL DIODES
1N6263
Figure D Buffer
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
14
TRADEMARKS
The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx®
Power247®
Green FPS™
Green FPS™ e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
SuperSOT™-8
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
SyncFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
Current Transfer Logic™
EcoSPARK®
QS™
®
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
FAST®
OPTOPLANAR®
FastvCore™
®
UniFET™
VCX™
FPS™
FRFET®
PDP-SPM™
Power220®
Global Power ResourceSM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I31
©2000 Fairchild Semiconductor Corporation
74OL60XX Rev. 1.0.4
www.fairchildsemi.com
15
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