74VCX132BQX [FAIRCHILD]
Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs; 低电压四2输入与非门施密特触发器输入和3.6V容限输入和输出
| 型号： | 74VCX132BQX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs |
| 文件： | 总10页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1999
Revised February 2005
74VCX132
Low Voltage Quad 2-Input NAND Gate
with Schmitt Trigger Inputs
and 3.6V Tolerant Inputs and Outputs
General Description
Features
The VCX132 contains four 2-input NAND gates with
Schmitt Trigger Inputs. The pin configuration and function
are the same as the VCX00 except the inputs have hyster-
esis between the positive-going and negative-going input
thresholds. This hysteresis is useful for transforming slowly
switching input signals into sharply defined, jitter-free out-
put signals. This product should be used where noise mar-
gin greater than that of conventional gates is required.
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD
3.3 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Static Drive (IOH/IOL
)
24 mA @ 3.0V VCC
The VCX132 is designed for low voltage (1.4V to 3.6V) VCC
applications with I/O compatibility up to 3.6V.
■ Uses patented Quiet Series noise/EMI reduction
circuitry
This product is fabricated with an advanced CMOS tech-
nology to achieve high-speed operation while maintaining
low CMOS power dissipation.
■ Latchup performance exceeds JEDEC 78 conditions
■ ESD performance:
Human body model 2000V
Machine model 250V
■ Leadless Pb-Free DQFN package
Ordering Code:
Order Number Package Number
Package Description
74VCX132M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VCX132BQX
(Note 1)
MLP014A
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74VCX132MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500164
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Logic Diagram
Connection Diagrams
Pin Assignments for SOIC and TSSOP
Pin Descriptions
Pin Name
Description
An, Bn
Inputs
On
Outputs
Pad Assignments for DQFN
(Top View)
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
DC Output Voltage (VO)
HIGH or LOW State (Note 3)
VCC 0V
Power Supply
Operating
1.4V to 3.6V
0.3V to 3.6V
0.5V to VCC 0.5V
0.5V to 4.6V
Input Voltage
Output Voltage (VO)
HIGH or LOW State
Output Current in IOH/IOL
VCC 3.0V to 3.6V
VCC 2.3V to 2.7V
VCC 1.65V to 2.3V
VCC 1.4V to 1.6V
Free Air Operating Temperature (TA)
DC Input Diode Current (IIK
VI 0V
)
0V to VCC
50 mA
DC Output Diode Current (IOK
VO 0V
)
24 mA
18 mA
50 mA
50 mA
VO VCC
6 mA
DC Output Source/Sink Current
(IOH/IOL
2 mA
)
50 mA
40 C to 85 C
DC VCC or Ground Current per
Supply Pin (ICC or Ground)
Note 2: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
100 mA
Storage Temperature (TSTG
)
65 C to 150 C
Note 3: I Absolute Maximum Rating must be observed.
O
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
3.6
V
V
V
V
HIGH Level Input Voltage
2.2
2.0
1.6
1.2
1.2
t
3.0
2.3
V
1.6
1.4
LOW Level Input Voltage
3.6
0.8
0.7
0.5
0.2
0.2
0.3
0.3
0.3
0.15
0.15
t
3.0
2.3
V
V
1.6
1.4
Input Hysteresis
3.6
1.2
1.2
1.0
0.9
0.9
H
3.0
2.3
1.6
1.4
HIGH Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
I
100
A
2.7 - 3.6
2.7
V
- 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
12 mA
18 mA
24mA
2.2
2.4
2.2
3.0
3.0
100
A
2.3 - 2.7
2.3
V
- 0.2
CC
6 mA
12 mA
18 mA
2.0
1.8
1.7
V
2.3
2.3
100
A
1.65 - 2.3
1.65
1.4 - 1.6
1.4
V
- 0.2
CC
6 mA
1.25
- 0.2
100
A
V
CC
2 mA
1.05
3
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DC Electrical Characteristics (Continued)
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
V
LOW Level Output Voltage
I
100
12
A
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
5.0
OL
OL
I
A
OL
I
18 mA
24 mA
3.0
OL
I
3.0
OL
I
100
A
2.3 - 2.7
2.3
OL
I
12 mA
18 mA
V
OL
I
2.3
OL
I
100
A
1.65 - 2.3
1.65
OL
I
6 mA
100
OL
I
A
1.4 - 1.6
1.4
OL
I
2 mA
OL
I
Input Leakage Current
0
V
V
3.6V
3.6V
1.4 - 3.6
A
A
A
A
A
I
I
I
3-STATE Output Leakage
0
OZ
O
1.4 - 3.6
10.0
V
0
V
or V
IH IL
I
I
Power Off Leakage Current
Quiescent Supply Current
(V , V )
O
3.6V
0
10.0
20.0
20.0
750
OFF
I
I
V
V
V
V
or GND
3.6V
I
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
CC
I
CC
V
CC
IH
I
Increase in I per Input
V
- 0.6V
CC
CC
CC
AC Electrical Characteristics (Note 5)
V
T
40 C to 85 C
Figure
CC
A
Symbol
Parameter
Propagation Delay
Conditions
Units
(V)
Min
Max
3.3
Number
t
t
C
30 pF, R
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.0
1.0
PHL
PLH
L
L
Figures
1, 2
4.1
ns
ns
8.2
C
C
15 pF, R
30 pF, R
2k
16.4
Figures
3, 4
L
L
t
t
Output-to-Output Skew
(Note 6)
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.5
0.5
OSHL
OSLH
L
L
0.75
1.5
C
15 pF, R
2k
L
L
Note 5: For C
50 pF, add approximately 300 ps to the AC maximum specification.
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).
L
OSHL
OSLH
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4
Dynamic Switching Characteristics
V
T
25 C
Typical
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
V
V
V
Quiet Output Dynamic Peak V
C
C
C
30 pF, V
30 pF, V
30 pF, V
V
V
V
, V
, V
, V
0V
0V
0V
0.25
0.6
0.8
0.25
0.6
OLP
OL
L
L
L
IH
IH
IH
CC
CC
CC
IL
IL
IL
V
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
OLV
OL
V
V
0.8
1.5
1.9
2.2
OHV
OH
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
Typical
6.0
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
0V or V , V
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
pF
pF
pF
IN
I
I
I
CC
CC
C
C
0V or V , V
7.0
OUT
PD
CC
CC
0V or V , f 10MHz, V
1.8V, 2.5V or 3.3V
20.0
CC
CC
AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)
CC
FIGURE 1. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
FIGURE 2. Waveform for Inverting and Non-inverting Functions
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
1.5V
VCC/2
VCC/2
5
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AC Loading and Waveforms (V 1.5V r 0.1V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
VCC x 2 at VCC 1.5V 0.1V
GND
t
PZL, tPLZ
tPZH, tPHZ
FIGURE 3. AC Test Circuit
FIGURE 4. Waveform for Inverting and Non-inverting Functions
VCC
Symbol
1.5V 0.1V
Vmi
VCC/2
VCC/2
Vmo
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6
Tape and Reel Specification
Tape Format for DQFN
Package
Tape
Section
Number
Cavities
125 (typ)
2500/3000
75 (typ)
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
BQX
Sealed
Trailer (Hub End)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
13.0
(330)
0.059
(1.50)
0.512
(13.00)
0.795
(20.20)
7.008
(178)
0.488
(12.4)
0.724
(18.4)
12 mm
7
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package Number MLP014A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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