74VCX16821 [FAIRCHILD]
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs; 低电压20位D型触发器具有3.6V容限输入和输出
| 型号： | 74VCX16821 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs |
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1998
Revised October 2004
74VCX16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16821 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
Features
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD
The 74VCX16821 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
3.5 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
The 74VCX16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Static Drive (IOH/IOL
)
±24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74VCX16821MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
Description
Output Enable Input (Active LOW)
CLKn
Clock Input
Inputs
D0–D19
O0–O19
Outputs
© 2004 Fairchild Semiconductor Corporation
DS500130
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Connection Diagram
Truth Tables
Inputs
OE1
Outputs
O0–O9
CLK1
D0–D9
X
H
L
L
L
X
L
Z
L
H
X
H
L or H
O0
Inputs
OE2
Outputs
O10–O19
CLK2
D10–D19
X
H
L
L
L
X
L
Z
L
H
X
H
L or H
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before LOW-to-HIGH transition of Clock
= LOW-to-HIGH transition
Functional Description
The VCX16821 contains twenty D-type flip-flops with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
each other. Control pins can be shorted together to obtain
full 20-bit operation. The following description applies to
each byte. The twenty flip-flops will store the state of their
individual D-type inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CLK) transition.
The 3-STATE standard outputs are controlled by the Out-
put Enable (OEn) input. When OEn is HIGH, the standard
outputs are in the high impedance mode but this does not
interfere with entering new data into the flip-flops.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.4V to 3.6V
Outputs 3-STATE
−0.5V to +4.6V
−0.5V to VCC + 0.5V
−50 mA
Input Voltage
−0.3V to +3.6V
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI < 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
Output Current in IOH/IOL
0V to VCC
DC Output Diode Current (IOK
)
0.0V to 3.6V
VO < 0V
−50 mA
+50 mA
VO > VCC
V
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
CC = 1.4V to 1.6V
±24 mA
±18 mA
DC Output Source/Sink Current
(IOH/IOL
)
±50 mA
±6 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
±2 mA
±100 mA
Free Air Operating Temperature (TA)
−40°C to +85°C
Storage Temperature Range (TSTG
)
−65°C to +150°C
Minimum Input Edge Rate (∆t/∆V)
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
2.7 - 3.6
2.3 - 2.7
2.0
1.6
V
1.65 - 2.3 0.65 x VCC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x VCC
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
0.7
V
0.35 x VCC
0.35 x VCC
VOH
I
I
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OH = −100 µA
OH = −6 mA
VCC - 0.2
2.2
3.0
2.4
3.0
2.2
2.3 - 2.7
2.3
VCC - 0.2
2.0
V
OH = −12 mA
OH = −18 mA
OH = −100 µA
OH = −6 mA
2.3
1.8
2.3
1.7
1.65 - 2.3
1.65
VCC - 0.2
1.25
OH = −100 µA
OH = −12 mA
1.4 - 1.6
1.4
VCC - 0.2
1.05
3
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DC Electrical Characteristics (Continued)
VCC
Symbol
VOL
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
LOW Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 24 mA
OL = 100 µA
OL = 6 mA
0.2
0.4
3.0
0.4
3.0
0.55
0.2
2.3 - 2.7
2.3
0.4
V
OL = 12 mA
OL = 100 µA
OL = 6 mA
2.3
0.6
1.65 - 2.3
1.65
0.2
0.3
OL = 100 µA
OL = 2 mA
1.4 - 1.6
1.4
0.2
0.35
±5.0
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
1.4 - 3.6
µA
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
1.4 - 3.6
±10
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
0
10
20
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
V
CC ≤ (VI, VO) ≤ 3.6V (Note 5)
IH = VCC −0.6V
±20
750
∆ICC
Increase in ICC per Input
V
Note 5: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 6)
VCC
TA = −40°C to +85°C
Figure
Symbol
fMAX
Parameter
Conditions
Units
(V)
Min
250
200
100
80.0
0.8
Max
Number
Maximum Clock Frequency
C
L = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
MHz
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tPHL
tPLH
Propagation Delay
Output Enable Time
Output Disable Time
C
3.5
4.4
Figures
1, 2
1.0
ns
ns
ns
1.5
8.8
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
1.0
17.6
Figures
7, 8
tPZL
tPZH
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.7
4.7
Figures
1, 3, 4
9.8
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
19.6
Figures
7, 9, 10
tPLZ
tPHZ
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.7
4.2
Figures
1, 3, 4
7.6
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
15.2
Figures
7, 9, 10
tS
Setup Time
Hold Time
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
1.5
1.5
2.5
3.0
1.0
1.0
1.0
2.0
1.5
1.5
4.0
4.0
ns
ns
ns
ns
Figure 6
Figure 6
Figure 5
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tH
C
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tW
Pulse Width
C
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tOSHL
tOSLH
Output to Output Skew
(Note 7)
C
0.5
0.5
0.75
1.5
C
L = 15 pF, RL = 500Ω
Note 6: For CL = 50 PF, add approximately 300 ps to the AC maximum specification.
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5
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Dynamic Switching Characteristics
VCC
T
A = +25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
−0.25
−0.6
−0.8
1.5
V
V
VOHV
1.9
2.2
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
CC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC
Units
Typical
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
6
7
pF
pF
pF
COUT
CPD
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz,
20
V
CC = 1.8V, 2.5V or 3.3V
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6
AC Loading and Waveforms (V 3.3V ± 0.3V to 1.8V ± 0.15V)
CC
TEST
tPLH, tPHL
tPZL, tPLZ
SWITCH
Open
6V at VCC = 3.3V ± 0.3V;
V
CC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
t
rec Waveforms
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.15V
V
OL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.15V
VOH − 0.15V
7
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AC Loading and Waveforms (V 1.5V ± 0.1V)
CC
TEST
PLH, tPHL
PZL, tPLZ
SWITCH
t
t
Open
VCC x 2 at VCC = 1.5V ± 0.1V
GND
tPZH, tPHZ
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and
Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V ± 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
V
OL + 0.1V
VY
VOH − 0.1V
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8
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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相关型号：
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