74VCX2245 [FAIRCHILD]
Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26W Series Resistors in B Outputs; 低电压双向收发器具有3.6V容限输入和输出， 26W系列电阻在B输出
| 型号： | 74VCX2245 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26W Series Resistors in B Outputs |
| 文件： | 总12页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
Revised April 2005
74VCX2245
Low Voltage Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistors in B Outputs
General Description
Features
The VCX2245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B ports
by placing them in a high impedance state.
■ 1.4V - 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ 26 series resistors in B Port outputs
■ Power-off high impedance inputs and outputs
■ Supports Live Insertion and Withdrawal (Note 1)
■ tPD (A to B)
The 74VCX2245 is designed for low voltage (1.4V to 3.6V)
VCC applications with I/O compatibility up to 3.6V. The
VCX2245 is also designed with 26 series resistance in
the B Port outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers transmitters
4.4 ns max for 3.0V to 3.6V VCC
■ Static Drive (IOH/IOL B outputs):
12 mA @ 3.0V VCC
The 74VCX2245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
■ Uses patented Quiet Series noise/EMI reduction
circuitry
■ Latchup performance exceeds JEDEC 78 conditions
■ ESD performance:
Human body model 2000V
Machine model 200V
■ Leadless DQFN Pb-Free package
Note 1: To ensure the high impedance state during power up and power
down, OE should be tied to V
through a pull up resistor. The minimum
CC
n
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Package
Order Number
Package Description
Number
74VCX2245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VCX2245BQX
(Note 2)
MLP020B
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
74VCX2245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2: DQFN package available in Tape and Reel only.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
T/R
Output Enable Input (Active LOW)
Transmit/Receive Input
A0–A7
B0–B7
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500170
www.fairchildsemi.com
Connection Diagrams
Truth Table
Pin Assignments for SOIC and TSSOP
Inputs
Outputs
OE T/R
L
L
L
H
X
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
H
HIGH Z State on A0–A7, B0–B7 (Note 3)
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Note 3: Unused bus terminals during HIGH Z State must be held HIGH or
LOW.
Logic Diagram
Pad Assignments for DQFN
(Top Through View)
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2
Absolute Maximum Ratings(Note 4)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply Voltage (VCC
Operating
)
DC Output Voltage (VO)
Outputs 3-STATE
1.4V to 3.6V
0.3V to 3.6V
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Input Voltage
Outputs Active (Note 5)
DC Input Diode Current (IIK) VI 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
0V to VCC
0V to 3.6V
DC Output Diode Current (IOK
VO 0V
)
50 mA
50 mA
50 mA
Output Current in IOH/IOL - A Outputs
VCC 3.0V to 3.6V
VO VCC
24 mA
18 mA
6 mA
DC Output Source/Sink Current
(IOH/IOL
VCC 2.3V to 2.7V
)
VCC 1.65V to 2.3V
DC VCC or Ground Current
Storage Temperature (TSTG
100 mA
VCC 1.4V to 1.65V
2 mA
)
65 C to 150 C
Output Current in IOH/IOL - B Outputs
VCC 3.0V to 3.6V
12 mA
8 mA
VCC 2.3V to 2.7V
VCC 1.65V to 2.3V
3 mA
VCC 1.4V to 1.65V
1 mA
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
V
V
V
HIGH Level Input Voltage
2.7 - 3.6
2.3 - 2.7
2.0
1.6
IH
V
1.65 - 2.3 0.65 x V
CC
CC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x V
LOW Level Input Voltage
0.8
0.7
IL
V
0.35 x V
0.35 x V
CC
CC
HIGH Level Output Voltage
A Outputs
I
I
I
I
I
I
I
I
I
I
I
I
100
A
V
- 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
12 mA
18 mA
24 mA
2.2
3.0
2.4
2.2
3.0
100
A
2.3 - 2.7
2.3
V
- 0.2
CC
6 mA
12 mA
18 mA
2.0
1.8
1.7
V
2.3
2.3
100
A
1.65 - 2.3
1.65
V
- 0.2
CC
8 mA
100
1.25
- 0.2
A
1.4 - 1.6
1.4
V
CC
2 mA
1.05
3
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DC Electrical Characteristics (Continued)
V
CC
Symbol
Parameter
Conditions
Min
- 0.2
Max
Units
(V)
2.7 - 3.6
2.7
V
HIGH Level Output Voltage
B Outputs
I
100
A
V
V
OH
OH
CC
I
6 mA
8 mA
2.2
2.4
2.2
OH
I
3.0
OH
I
12 mA
3.0
OH
I
100
A
2.3 - 2.7
2.3
- 0.2
CC
OH
I
4 mA
6 mA
8 mA
100
2.0
1.8
1.7
OH
V
I
2.3
OH
I
2.3
OH
I
A
1.65 - 2.3
1.65
V
V
- 0.2
CC
OH
I
3 mA
100
1.25
- 0.2
CC
OH
I
A
1.4 - 1.6
1.4
OH
I
1 mA
1.05
OH
V
LOW Level Output Voltage
A Outputs
I
100
A
2.7 - 3.6
2.7
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
0.2
0.4
0.55
0.8
0.2
0.4
0.6
0.2
0.3
0.2
0.35
5.0
OL
OL
I
12 mA
18 mA
24 mA
OL
I
3.0
OL
I
3.0
OL
I
100
A
2.3 - 2.7
2.3
OL
I
12 mA
18 mA
V
OL
I
2.3
OL
I
100
A
1.65 - 2.3
1.65
OL
I
6 mA
100
OL
I
A
A
1.4 - 1.6
1.4
OL
I
2 mA
100
OL
V
LOW Level Output Voltage
B Outputs
I
2.7 - 3.6
2.7
OL
OL
I
6 mA
8 mA
OL
I
3.0
OL
I
12 mA
3.0
OL
I
100
A
2.7- 2.7
2.3
OL
I
6 mA
8 mA
100
V
OL
I
2.3
OL
I
A
A
1.65 - 2.3
1.65
OL
I
3 mA
100
OL
I
1.4 - 1.6
1.4
OL
I
1 mA
OL
I
Input Leakage Current
0
V
V
3.6V
3.6V
1.4 - 3.6
A
A
A
A
A
I
I
I
3-STATE Output Leakage
0
OZ
O
1.4 - 3.6
10
V
0
V
or V
IH IL
I
I
Power Off Leakage Current
Quiescent Supply Current
(V , V )
3.6V
V or GND
CC
0
10
20
OFF
I
O
I
V
V
V
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
CC
I
(V , V )
O
3.6V (Note 7)
20
CC
IH
I
I
Increase in I per Input
V 0.6V
CC
750
CC
CC
Note 7: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 8)
V
T
40 C to 85 C
Figure
CC
A
Symbol
Parameter
Conditions
Units
(V)
Min
Max
3.5
Number
t
t
Propagation Delay
to A
C
30 pF, R
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.5
1.0
PHL
L
L
Figures
1, 2
B
4.2
PLH
n
n
ns
8.4
C
C
15 pF, R
30 pF, R
2k
16.8
Figures
5, 6
L
L
t
t
Output Enable Time
to A
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.5
1.0
4.5
5.6
PZL
PZH
L
L
Figures
1, 3, 4
B
n
n
ns
9.8
C
C
15 pF, R
30 pF, R
2k
19.6
Figures
5, 7, 8
L
L
t
t
Output Disable Time
to A
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.5
1.0
3.6
4.0
PLZ
PHZ
L
L
Figures
1, 3, 4
B
n
n
ns
ns
ns
7.2
C
C
15 pF, R
30 pF, R
2k
14.4
Figures
5, 7, 8
L
L
t
t
Output to Output Skew
(Note 9)
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.5
0.5
OSHL
OSLH
L
L
0.75
1.5
C
C
15 pF, R
30 pF, R
2k
L
L
t
t
Propagation Delay
500
0.6
0.8
1.5
1.0
4.4
PHL
PLH
L
L
Figures
1, 2
A
to B
5.6
n
n
9.8
C
C
15 pF, R
30 pF, R
2k
19.6
Figures
5, 6
L
L
t
t
Output Enable Time
to B
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.5
1.0
5.0
6.6
PZL
PZH
L
L
Figures
1, 3, 4
A
n
n
ns
ns
9.8
C
C
15 pF, R
30 pF, R
2k
19.6
Figures
5, 7, 8
L
L
t
t
Output Disable Time
to B
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.6
0.8
1.5
1.0
4.2
4.7
PLZ
PHZ
L
L
Figures
1, 3, 4
A
n
n
8.5
C
15 pF, R
2k
16.9
Figures
5, 7, 8
L
L
Note 8: For C
50 pF, add approximately 300 ps to the AC maximum specification.
L
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
5
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Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.3
V
V
V
Quiet Output Dynamic Peak V
B to A
,
C
C
C
C
C
C
30 pF, V
30 pF, V
30 pF, V
30 pF, V
30 pF, V
30 pF, V
V
V
V
V
V
V
, V
, V
, V
, V
, V
, V
0V
0V
0V
0V
0V
0V
OLP
OL
OL
L
L
L
L
L
L
IH
IH
IH
IH
IH
IH
CC
CC
CC
CC
CC
CC
IL
0.7
V
1.0
Quiet Output Dynamic Peak V
A to B
,
0.2
IL
0.45
0.65
0.3
V
V
V
V
V
Quiet Output Dynamic Valley V
B to A
,
OLV
OL
IL
0.7
1.0
Quiet Output Dynamic Valley, V
A to B
,
0.2
OL
IL
IL
IL
0.45
0.65
1.3
Quiet Output Dynamic Valley V
B to A
,
OHV
OH
1.7
2.0
Quiet Output Dynamic Valley V
A to B
,
1.5
OH
2.0
2.5
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
Typical
C
Input Capacitance
V
V
V
0V or V , V
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
6
7
pF
pF
pF
IN
I
I
I
CC
CC
C
C
Input/Output Capacitance
0V or V , V
CC
I/O
PD
CC
Power Dissipation Capacitance
0V or V , f 10 MHz, V
CC
1.8V, 2.5V or 3.3V
20
CC
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6
AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)
CC
FIGURE 1. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
6V at VCC 3.3 0.3V;
VCC x 2 at VCC 2.5V 0.2V; 1.8V 0.15V
GND
tPZL, tPLZ
tPZH, tPHZ
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
Vx
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
VOL 0.15V
VOH 0.15V
Vy
7
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AC Loading and Waveforms (V 1.5V r 0.1V)
CC
FIGURE 5. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
VCC x 2 at VCC 1.5V 0.1V
GND
tPZL, tPLZ
tPZH, tPHZ
FIGURE 6. Waveform for Inverting and Non-inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V 0.1V
Vmi
Vmo
Vx
VCC/2
VCC/2
VOL 0.1V
VOH 0.1V
Vy
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8
Tape and Reel Specification
Tape Format for DQFN
Package
Tape
Section
Number
Cavities
125 (typ)
2500/3000
75 (typ)
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
BQX
Sealed
Trailer (Hub End)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
13.0
(330)
0.059
(1.50)
0.512
(13.00)
0.795
(20.20)
7.008
(178)
0.488
(12.4)
0.724
(18.4)
12 mm
9
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package Number MLP020B
11
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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12
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