74VCXH162373_05 [FAIRCHILD]
Low Voltage 16-Bit Transparent Latch with Bushold and 26ohm Series Resistors in Outputs; 低电压16位透明锁存器与Bushold和26ohm串联电阻的输出
| 型号： | 74VCXH162373_05 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 16-Bit Transparent Latch with Bushold and 26ohm Series Resistors in Outputs |
| 文件： | 总9页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2000
Revised June 2005
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26: Series Resistors in Outputs
General Description
Features
■ 1.4V to 3.6V VCC supply operation
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26 series resistors in outputs
■ tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
The VCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
■ Static Drive (IOH/IOL
)
12 mA @ 3.0V VCC
The VCXH162373 is also designed with 26 series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model 2000V
The 74VCXH162373 is designed for low voltage (1.4V to
3.6V) VCC applications with output compatibility up to 3.6V.
Machine model 200V
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Package
Ordering Number
Number
Package Description
74VCXH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74VCXH162373MTX
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
LEn
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
I0–I15
O0–O15
Outputs
© 2005 Fairchild Semiconductor Corporation
DS500227
www.fairchildsemi.com
Connection Diagram
Truth Tables
Inputs
OE1
Outputs
O0–O7
LE1
I0–I7
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
Inputs
OE2
Outputs
O8–O15
LE2
I8–I15
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O0
H
L
HIGH Voltage Level
LOW Voltage Level
X
Z
O
Immaterial (HIGH or LOW, control inputs may not float)
High Impedance
Previous O before HIGH-to-LOW of Latch Enable
0
0
Functional Description
The 74VCXH162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The
3-STATE outputs are controlled by the Output Enable
(OEn) input. When OEn is LOW the standard outputs are in
the 2-state mode. When OEn is HIGH, the standard outputs
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC
)
0.5V to 4.6V
0.5V to 4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.4V to 3.6V
0.3V to VCC
Outputs 3-STATED
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Input Voltage
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
0V to VCC
DC Output Diode Current (IOK
VO 0V
)
0.0V to 3.6V
50 mA
50 mA
Output Current in IOH/IOL
VCC 3.0V to 3.6V
VO VCC
12 mA
8 mA
DC Output Source/Sink Current
(IOH/IOL
VCC 2.3V to 2.7V
)
50 mA
VCC 1.65V to 2.3V
VCC 1.4V to 1.6V
3 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
1 mA
100 mA
Free Air Operating Temperature (TA)
Minimum Input Edge Rate ( t/ V)
VIN 0.8V to 2.0V, VCC 3.0V
40 C to 85 C
Storage Temperature Range (TSTG
)
65 C to 150 C
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3: I Absolute Maximum Rating must be observed.
O
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
V
CC
Symbol
Parameter
HIGH Level Input Voltage
Conditions
Min
Max
Units
(V)
V
V
V
2.7 - 3.6
2.3 - 2.7
2.0
1.6
IH
V
1.65 - 2.3 0.65 x V
CC
CC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x V
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
0.7
IL
V
0.35 x V
0.35 x V
CC
CC
I
I
I
I
I
I
I
I
I
I
I
I
100
A
V
- 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
6 mA
8 mA
2.2
3.0
2.4
2.2
12 mA
3.0
100
A
2.7 - 3.6
2.3
V
- 0.2
CC
4 mA
6 mA
8 mA
100
2.0
1.8
1.7
V
2.3
2.3
A
A
1.65 - 2.3
1.65
V
- 0.2
CC
3 mA
100
1.25
- 0.2
1.4 - 1.6
1.4
V
CC
1 mA
1.05
3
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DC Electrical Characteristics (Continued)
V
CC
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
V
LOW Level Output Voltage
I
100
A
0.2
0.4
0.55
0.8
0.2
0.4
0.6
0.2
0.3
0.2
0.35
5.0
5.0
OL
OL
I
6 mA
8 mA
12 mA
OL
I
3.0
OL
I
3.0
OL
I
100
A
2.3 - 2.7
2.3
OL
I
6 mA
8 mA
100
V
OL
I
2.3
OL
I
A
A
1.65 - 2.3
1.65
1.4 - 1.6
1.4
OL
I
3 mA
100
OL
I
OL
I
1 mA
OL
I
Input Leakage Current
Control Pins
Data Pins
0
V
3.6V
V or GND
CC
1.4 - 3.6
1.4 - 3.6
3.0
A
A
I
I
V
V
V
V
V
V
V
I
I
Bushold Input Minimum
Drive Hold Current
0.8V
2.0V
0.7V
1.6V
0.57V
1.07V
75
75
I(HOLD)
IN
IN
IN
IN
IN
IN
3.0
2.3
45
A
A
2.3
45
1.65
1.65
3.6
25
25
I
Bushold Input Over-Drive
Current to Change State
(Note 5)
(Note 6)
(Note 5)
(Note 6)
(Note 5)
(Note 6)
450
450
300
300
200
200
I(OD)
3.6
2.7
2.7
1.95
1.95
I
3-STATE Output Leakage
0
V
0
V
3.6V
or V
OZ
O
1.4 - 3.6
10
A
A
A
A
V
I
IH
IL
I
Power-OFF Leakage Current
Quiescent Supply Current
(V
V
)
3.6V
0
10
20
OFF
O
I
V
or GND
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
CC
I
CC
(V
V
V
)
O
3.6V (Note 7)
0.6V
20
CC
IH
I
Increase in I per Input
V
750
CC
CC
CC
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: Outputs disabled or 3-STATE only.
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4
AC Electrical Characteristics (Note 8)
V
T
40 C to 85 C
Figure
CC
A
Symbol
Parameter
Conditions
Units
(V)
Min
Max
3.3
Number
t
t
Propagation Delay
to O
C
30 pF, R
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
PHL
L
L
Figures
1, 2
I
4.5
PLH
n
n
ns
9.0
C
C
30 pF, R
30 pF, R
2k
18.0
Figures
7, 8
L
L
t
t
Propagation Delay
LE to O
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
3.6
4.9
PHL
PLH
L
L
Figures
1, 2
n
ns
ns
ns
9.8
C
C
30 pF, R
30 pF, R
500
500
19.6
Figures
7, 8
L
L
t
t
Output Enable Time
Output Disable Time
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
3.9
5.4
PZL
PZH
L
L
Figures
1, 3, 4
9.8
C
C
30 pF, R
30 pF, R
2k
19.6
Figures
7, 9, 10
L
L
t
t
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
0.8
1.0
1.5
1.0
4.0
4.4
PLZ
PHZ
L
L
Figures
1, 3, 4
7.9
C
C
30 pF, R
30 pF, R
2k
15.8
Figures
7, 9, 10
L
L
t
t
t
Setup Time
Hold Time
Pulse Width
500
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
3.3 0.3
2.5 0.2
1.8 0.15
1.5 0.1
1.5
1.5
2.5
3.0
1.0
1.0
1.0
2.0
1.5
1.5
4.0
4.0
S
L
L
ns
ns
ns
ns
Figure 6
Figure 6
Figure 5
C
C
30 pF, R
30 pF, R
500
500
L
L
H
W
L
L
C
C
30 pF, R
30 pF, R
500
500
L
L
L
L
C
C
30 pF, R
30 pF, R
500
500
L
L
t
t
Output to Output Skew
(Note 9)
0.5
0.5
OSHL
OSLH
L
L
0.75
1.5
C
30 pF, R
2k
L
L
Note 8: For C
50 F, add approximately 300 ps to the AC maximum specification.
P
L
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSLH
OSHL
5
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Dynamic Switching Characteristics
V
T
25 C
Typical
CC
A
Symbol
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
V
V
V
Quiet Output Dynamic Peak V
C
C
C
30 pF, V
30 pF, V
30 pF, V
V
V
V
, V
, V
, V
0V
0V
0V
0.15
0.25
0.35
0.15
0.25
0.35
1.55
2.05
2.65
OLP
OL
L
L
L
IH
IH
IH
CC
CC
CC
IL
IL
IL
V
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
OLV
OL
V
V
OHV
OH
Capacitance
T
25 C
A
Symbol
Parameter
Conditions
Units
Typical
C
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
V
V
V
1.8V, 2.5V or 3.3V, V 0V or V
CC
6
7
pF
pF
pF
IN
CC
I
C
0V or V , V
CC
1.8V, 2.5V or 3.3V
OUT
PD
I
CC
C
0V or V , f 10 MHz,
CC
20
I
1.8V, 2.5V or 3.3V
CC
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6
AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)
CC
TEST
SWITCH
Open
t
PLH, tPHL
tPZL, tPLZ
6V at VCC 3.V3 0.3V;
VCC x 2 at VCC 2.V5 0.2V; 1.8V 0.15V
GND
tPZH, tPHZ
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
VCC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
VCC/2
1.8V 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
VOL 0.3V
VOH 0.3V
VOL 0.15V
VOH 0.15V
VOL 0.15V
VOH 0.15V
VY
7
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AC Loading and Waveforms (V 1.5V r 0.1V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
VCC x 2 at VCC 1.5 0.1V
GND
t
PZL, tPLZ
tPZH, tPHZ
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
VOL 0.1V
VOH 0.1V
VY
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8
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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