74VHC123ASJX [FAIRCHILD]
Monostable Multivibrator ; 单稳态多谐振荡器\n
| 型号： | 74VHC123ASJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Monostable Multivibrator
|
| 文件： | 总9页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1993
Revised April 1999
74VHC123A
Dual Retriggerable Monostable Multivibrator
An input protection circuit ensures that 0 to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
General Description
The VHC123A is an advanced high speed CMOS
Monostable Multivibrator fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Each multivibrator features
both a negative, A, and a positive, B, transition triggered
input, either of which can be used as an inhibit input. Also
included is a clear input that when taken low resets the
one-shot. The VHC123A can be triggered on the positive
transition of the clear while A is held low and B is held high.
The output pulse width is determined by the equation:
PW = (Rx)(Cx); where PW is in seconds, R is in ohms, and
Features
■ High Speed:
t
PD = 8.1 ns (typ) at TA = 25°C
■ Low Power Dissipation:
CC = 4 µA (Max) at TA = 25°C
I
C is in farads.
■ Active State: ICC = 600 µA (Max) at TA = 25°C
Limits for Rx and Cx are:
■ High Noise Immunity: VNIH = VNIL = 28% VCC (min)
External capacitor, Cx No limit
■ Power down protection is provided on all inputs
■ Pin and function compatible with 74HC123A
External resistors, Rx
CC > 3.0V, 1 kΩ min
VCC = 2.0V, 5 kΩ min
V
Ordering Code:
Order Number Package Number
Package Description
74VHC123AM
74VHC123ASJ
74VHC123AMTC
74VHC123AN
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS011621.prf
www.fairchildsemi.com
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
Function
A
Trigger Inputs (Negative Edge)
Trigger Inputs (Positive Edge)
Reset Inputs
A
B
H
L
CLR
H
Q
Q
B
Output Enable
Inhibit
CLR
Cx
X
H
L
H
L
L
H
H
External Capacitor
External Resistor
X
H
Inhibit
Rx
H
Output Enable
Output Enable
Reset
Q, Q
Outputs
L
H
X
X
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH-to-LOW Transition
= LOW-to-HIGH Transition
Block Diagrams
Note A: C , R , D are external Capacitor, Resistor, and Diode, respectively.
x
x
x
Note B: External clamping diode, D ;
x
External capacitor is charged to V level in the wait state, i.e. when no trigger is applied.
CC
If the supply voltage is turned off, C discharges mainly through the internal (parasitic) diode. If C is sufficiently large and V drops rapidly, there will be
CC
x
x
some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and V drops slowly,
CC
the in rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20 mA. In the case of a large Cx, the limit of fall time of the supply voltage is deter-
mined as follows:
t
≥ (V −0.7) C /20 mA
CC x
f
(t is the time between the supply voltage turn off and the supply voltage reaching 0.4 V
)
f
CC
In the event a system does not satisfy the above condition, an external clamping diode (D ) is needed to protect the IC from rush current.
x
System Diagram
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2
Timing Chart
Functional Description
1. Stand-by State
voltage VrefH, the output of C2 becomes LOW, the out-
put Q goes LOW and C2 stops its operation. That
The external capacitor (Cx) is fully charged to VCC in
means, after triggering, when the voltage level of the
Rx/Cx node reaches VrefH, the IC returns to its
the Stand-by State. That means, before triggering, the
QP and QN transistors which are connected to the Rx/
MONOSTABLE state.
Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply current
is only leakage current.
With large values of Cx and Rx, and ignoring the dis-
charge time of the capacitor and internal delays of the
IC, the width of the output pulse, tW (OUT), is as fol-
2. Trigger Operation
lows:
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling signal;
and third, where the A input is LOW and the B input is
HIGH, and the CLR input has a rising signal.
tW (OUT) = 1.0 Cx Rx
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging Cx. The voltage level of the Rx/Cx
node then falls to VrefL level again. Therefore the Q
After a trigger becomes effective, comparators C1 and
C2 start operating, and QN is turned on. The external
capacitor discharges through QN. The voltage level at
the Rx/Cx node drops. If the Rx/Cx voltage level falls to
the internal reference voltage VrefL, the output of C1
becomes LOW. The flip-flop is then reset and QN turns
off. At that moment C1 stops but C2 continues operat-
ing.
output stays HIGH if the next trigger comes in before
the time period set by Cx and Rx.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd trig-
ger, tRR (Min), depends on VCC and Cx.
4. Reset Operation
After QN turns off, the voltage at the Rx/Cx node starts
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q out-
put is held LOW and the trigger control F/F is reset.
rising at a rate determined by the time constant of
external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of Rx/Cx changes from falling
Also, Qp turns on and Cx is charged rapidly to VCC
.
This means if CLR is set LOW, the IC goes into a wait
state.
to rising. When Rx/Cx reaches the internal reference
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5 to VCC +0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature
(Topr
)
2.0V to +5.5V
0V to +5.5V
0V to VCC
)
)
)
)
)
±20 mA
)
±25 mA
)
−40° to +85°C
)
±50 mA
Input Rise and Fall Time (tr, tf)
(CLR only)
Storage Temperature (TSTG
Lead Temperature (TL)
Soldering, 10 seconds
)
−65°C to 150°C
V
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0
100 ns/V
20 ns/V
260°C
0
External Capacitor - Cx
External Resistor - Rx
No Limitation (Note 3) F
>5 kΩ (Note 3) (VCC = 2.0V)
>1 kΩ (Note 3) (VCC > 3.0V)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommended operation outside data book speci-
fications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Note 3: The maximum allowable values of C and R are a function of the
x
x
leakage of capacitor C , the leakage of the device, and leakage due to
x
board layout and surface resistance. Susceptibility to externally induced
noise signals may occur for R > 1 MΩ.
x
DC Electrical Characteristics
T
= 25°C
T = −40° to 85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
Max
V
V
V
HIGH Level
2.0
1.50
1.50
IH
V
V
Input Voltage
LOW Level
3.0 − 5.5 0.7 V
2.0
0.7 V
CC
CC
0.50
0.50
IL
Input Voltage
HIGH Level
Output Voltage
3.0 − 5.5
0.3 V
0.3 V
CC
CC
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
4.5
V
LOW Level
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN IH
OL
Output Voltage
3.0
or V
IL
4.5
0.1
0.1
V
3.0
0.36
0.36
±0.1
±0.25
0.44
0.44
±1.0
±2.50
I
I
= 4 mA
= 8 mA
OL
OL
4.5
I
Input Leakage Current
0 − 5.5
5.5
µA
µA
V
V
= 5.5V or GND
IN
IN
I
R /C Terminal
= V or GND
CC
IN
x
x
IN
Off-State Current
Quiescent Supply Current
Active—State
I
5.5
3.0
4.5
5.5
4.0
250
500
750
40.0
280
650
975
µA
µA
V
= V or GND
CC
CC
IN
I
160
380
560
V
= V or GND
CC
CC
IN
(Note 4)
R /C = 0.5 V
x x CC
Supply Current
Note 4: Per Circuit
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4
AC Electrical Characteristics (Note 5)
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
= 15 pF
Min
Typ
13.4
15.9
Max
20.6
24.1
Min
Max
24.0
27.5
t
t
Propagation Delay Time 3.3 ± 0.3
1.0
C
PLH
L
ns
ns
ns
ns
ns
ns
ns
µs
ms
PHL
1.0
C
= 50 pF
(A, B–Q, Q)
L
5.0 ± 0.5
8.1
9.6
12.0
14.0
22.4
25.9
1.0
1.0
1.0
1.0
14.0
16.0
26.0
29.5
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
L
L
L
L
t
t
Propagation Delay Time 3.3 ± 0.3
14.5
17.0
PLH
PHL
(CLR Trigger—Q, Q \)
5.0 ± 0.5
8.7
12.9
14.9
15.8
19.3
1.0
1.0
1.0
1.0
15.0
17.0
18.5
22.0
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
L
L
L
L
10.2
10.3
12.8
t
t
Propagation Delay Time 3.3 ± 0.3
PLH
PHL
(CLR—Q, Q)
5.0 ± 0.5
6.3
7.8
9.4
11.4
240
200
110
110
1.1
1.0
1.0
11.0
13.0
300
240
110
110
1.1
C
C
C
= 15 pF
= 50 pF
= 50 pF
L
L
L
t
Output Pulse Width
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
160
133
100
100
1.0
C
R
C
R
C
R
= 28 pF
= 2 kΩ
WOUT
x
x
x
x
x
x
90
90
90
90
C
= 50 pF
= 50 pF
= 0.01 µF
= 10 kΩ
= 0.1 µF
= 10 kΩ
L
L
0.9
0.9
0.9
0.9
C
1.0
1.1
1.1
∆t
Output Pulse Width Error
Between Circuits
(In same Package)
Input Capacitance
Power Dissipation
Capacitance
WOUT
±1
%
C
C
4
10
10
pF
pF
V
= Open
IN
CC
73
(Note 6)
PD
Note 5: Refer to Timing Chart.
Note 6: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation:
1
I
(opr.) = C *V *f
I
*Duty/100 + I /2 (per Circuit)
CC
PD CC IN+ CC CC
1
I
: Active Supply Current
CC
Duty:%
AC Operating Requirement (Note 7)
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
5.0
5.0
5.0
5.0
Typ
Max
Min
Max
t
(L)
(H)
(L)
Minimum Trigger
3.3
5.0
5.0
5.0
5.0
5.0
W
ns
ns
t
Pulse Width
Minimum Clear
Pulse Width
Minimum
W
t
3.3
W
5.0
t
3.3 ± 0.3
5.0 ± 0.5
3.3
60
39
ns
R
C
R
C
= 1 kΩ
RR
x
Retrigger Time
= 100 pF
= 1 kΩ
X
x
1.5
1.2
µs
5.0
= 0.01 µF
X
Note 7: Refer to Timing Chart.
5
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Device Characteristics
twout*Cx Characteristics (typ)
tRR*VCC Characteristics (typ)
Output Pulse Width Constant K-Supply Voltage
(Typical)
Input Equivalent Circuit
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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