74VHC175MX [FAIRCHILD]
Quad D-Type Flip-Flop ; 四D型触发器\n
| 型号： | 74VHC175MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad D-Type Flip-Flop
|
| 文件： | 总7页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
Revised April 1999
74VHC175
Quad D-Type Flip-Flop
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
Features
■ High Speed: fMAX = 210 MHz (typ) at VCC = 5V
■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
■ Power down protection is provided on all inputs
■ Low noise: VOLP = 0.8V (max)
■ Pin and function compatible with 74HC175
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
Ordering Code:
Order Number Package Number
Package Description
74VHC175M
74VHC175SJ
74VHC175MTC
74VHC175N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D3
CP
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
MR
Q0–Q3
Q0–Q 3
Complement Outputs
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS011637.prf
www.fairchildsemi.com
Functional Description
Truth Table
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will store
the state of their individual D inputs on the LOW-to-HIGH
clock (CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force all
Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The VHC175 is useful for general logic
applications where a common Master Reset and Clock are
acceptable.
Inputs
Outputs
@ tn+1
@ tn, MR = H
Dn
Qn
Qn
L
L
H
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
t
= Bit Time before Clock Pulse
n
t
= Bit Time after Clock Pulse
n+1
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to +5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±50 mA
V
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 − 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
IL
3.0 − 5.5
0.3 V
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
4.5
V
LOW Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN
OL
IH
3.0
or V
IL
4.5
0.1
0.1
3.0
0.36
0.36
±0.1
4.0
0.44
0.44
±1.0
40.0
I
I
= 4 mA
= 8 mA
OL
OL
4.5
I
I
Input Leakage Current
0 − 5.5
5.5
µA
µA
V
V
= 5.5V or GND
IN
CC
IN
Quiescent Supply Current
= V or GND
IN
CC
Noise Characteristics
T
= 25°C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum Dynamic V
5.0
0.4
0.8
V
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
OL
L
L
L
L
(Note 3)
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
−0.4
−0.8
3.5
V
V
V
OLV
OL
(Note 3)
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
(Note 3)
V
1.5
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
MHz
MHz
ns
Conditions
= 15 pF
Min
90
Typ
140
75
Max
Min
Max
f
Maximum Clock
3.3 ± 0.3
75
45
C
C
C
C
C
C
MAX
L
L
L
L
L
L
Frequency
50
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
5.0 ± 0.5
3.3 ± 0.3
150
85
210
115
7.5
125
75
t
Propagation Delay
11.5
15.0
1.0
1.0
13.5
17.0
PLH
10.0
t
Time (CP to Q or Q )
PHL
n
n
5.0 ± 0.5
3.3 ± 0.3
4.8
6.3
6.3
8.8
7.3
9.3
1.0
1.0
1.0
1.0
8.5
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
L
L
L
L
ns
10.5
12.0
15.5
t
Propagation Delay Time
(MR to Q or Q )
10.1
13.6
PLH
ns
t
PHL
n
n
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
4.3
5.8
6.4
8.4
1.5
1.0
1.0
7.5
9.5
1.5
C
C
C
= 15 pF
= 50 pF
= 50 pF
L
L
L
ns
t
Output to
Output Skew
OSLH
t
OSHL
1.0
10
1.0
10
C
= 50 pF
L
(Note 4)
V = Open
CC
C
Input Capacitance
Power Dissipation
Capacitance
4
pF
pF
IN
C
44
(Note 5)
PD
Note 4: Parameter guaranteed by design. t
= |t
− t
|; t
=| t
− t
|.
PHLmin
OSLH
PLHmax
PLHmin OSHL
PHLmax
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.) = C * V * f + I /4 (per F/F), and the total C when n pcs of the Flip-Flop operate can
CC
PD
CC
IN
CC
PD
be calculated by the following equation: C (total) = 30 + 14 • n
PD
AC Operating Requirements
V
T
= 25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Minimum Pulse Width (CP)
Units
(V)
(Note 6)
Typ
Guaranteed Minimum
t
t
t
(L)
(H)
(L)
3.3
5.0
3.3
5.0
5.0
5.0
5.0
W
W
W
ns
ns
ns
ns
ns
5.0
5.0
Minimum Pulse Width (MR)
5.0
3.3
5.0
3.3
5.0
3.3
5.0
5.0
4.0
1.0
1.0
5.0
5.0
5.0
4.0
1.0
1.0
5.0
t
t
t
Minimum Setup Time (Dn to CP)
Minimum Hold Time (Dn to CP)
S
H
Minimum Removal Time (MR)
REC
5.0
5.0
5.0
Note 6:
V
is 3.3 ± 0.3V or 5.0 ± 0.5V
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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