74VHC374M [FAIRCHILD]
Octal D-Type Flip-Flop with 3-STATE Outputs; 八路D型IP- FL佛罗里达州运与三态输出
| 型号： | 74VHC374M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Flip-Flop with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1992
Revised April 1999
74VHC374
Octal D-Type Flip-Flop with 3-STATE Outputs
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
General Description
The VHC374 is an advanced high speed CMOS octal flip-
flop with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP) and an output enable input
(OE). When the OE input is HIGH, the eight outputs are in
a HIGH impedance state.
Features
■ High Speed: tPD = 5.4 ns (typ) at VCC = 5V
■ High noise immunity: VNIH = VNIL = 28% VCC (Min)
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC = 4 µA (Max) @ TA = 25°C
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
■ Pin and function compatible with 74HC374
Ordering Code:
Order Number Package Number
Package Description
74VHC374M
74VHC374SJ
74VHC374MTC
74VHC374N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
© 1999 Fairchild Semiconductor Corporation
DS011538.prf
www.fairchildsemi.com
Functional Description
Truth Table
The VHC374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Inputs
Outputs
Dn
H
L
CP
OE
L
On
H
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to +5.5V
0V to +5.5V
)
)
Input Diode Current (IIK
Output Diode Current
)
)
0V to VCC
±20 mA
)
−40°C to +85°C
DC Output Current (IOUT
)
±25 mA
DC VCC/GND Current (ICC
)
±75 mA
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0 ns/V – 100 ns/V
0 ns/V – 20 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 − 5.5 0.7 V
2.0
CC
CC
LOW Level Input Voltage
0.50
0.50
IL
3.0 − 5.5
0.3 V
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
V
LOW Level Output
Voltage
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN IH
OL
or V
IL
0.1
0.1
0.36
0.36
±0.25
0.44
0.44
±2.5
I
I
= 4 mA
= 8 mA
OL
OL
V
I
3-STATE Output
µA
V
V
V
V
= V or V
IH IL
OZ
IN
Off-State Current
= V or GND
CC
OUT
I
I
Input Leakage Current
Quiescent Supply Current
0 − 5.5
±0.1
±1.0
µA
µA
= 5.5V or GND
IN
IN
IN
5.5
4.0
40.0
= V or GND
CC
CC
Noise Characteristics
T
= 25°C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum Dynamic V
5.0
0.6
0.9
V
V
V
V
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
OL
L
(Note 3)
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
−0.6
−0.9
3.5
C
L
OLV
OL
(Note 3)
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
C
C
IHD
L
L
(Note 3)
V
1.5
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
3
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AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Typ
8.1
Max
12.7
16.2
8.1
Min
Max
15.0
18.5
9.5
t
Propagation Delay Time
3.3 ± 0.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
t
(CP to O )
n
10.6
5.4
PHL
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
ns
6.9
10.1
11.0
14.5
7.6
11.5
13.0
16.5
9.0
t
3-STATE Output
Enable Time
7.1
R
R
= 1 kΩ
= 1 kΩ
PZL
L
ns
t
9.6
PZH
5.1
ns
6.6
9.6
11.0
16.0
10.0
1.5
t
3-STATE Output
Disable Time
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
10.2
6.1
14.0
8.8
PLZ
L
ns
t
PHZ
t
Output to Output Skew
1.5
(Note 4)
OSLH
ns
t
1.0
1.0
OSHL
f
Maximum Clock Frequency 3.3 ± 0.3
80
55
130
85
185
120
4
70
50
MAX
MHz
5.0 ± 0.5
130
85
110
75
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
10
10
pF
pF
pF
V
V
= Open
= 5.0V
IN
CC
CC
C
C
6
OUT
PD
32
(Note 5)
Note 4: Parameter guaranteed by design. t
= |t
− t
|; t
= |t
− t
|
OSLH
PLH max
PLH min OSHL
PHL max
PHL min
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.) = C * V * f + I /8 (per F/F). The total C when n pcs. of the Octal D Flip-Flop operates
CC
PD
CC
IN
CC
PD
can be calculated by the equation: C (total) = 20 + 12n.
PD
AC Operating Requirements
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Minimum Pulse Width (CP)
Units
ns
Min
5.0
5.0
4.5
3.0
2.0
2.0
Typ
Max
Min
Max
t
(H)
(L)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
5.5
5.0
4.5
3.0
2.0
2.0
W
t
W
t
Minimum Set-Up Time
Minimum Hold Time
S
ns
t
ns
H
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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