74VHC4066 [FAIRCHILD]
Quad Analog Switch; 四路模拟开关
| 型号： | 74VHC4066 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad Analog Switch |
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1994
Revised January 2000
74VHC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches uti-
lizing advanced silicon-gate CMOS technology. These
switches have low “on” resistance and low “off” leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the 4066
switches contain linearization circuitry which lowers the
“on” resistance and increases switch linearity. The 4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to VCC and
■ Typical switch enable time: 15 ns
■ Wide analog input voltage range: 0–12V
■ Low “on” resistance: 30 typ. ('4066)
■ Low quiescent current: 80 µA maximum (74VHC)
■ Matched switch characteristics
■ Individual switch controls
■ Pin and function compatible with the 74HC4066
ground.
Ordering Code:
Order Number Package Number
Package Description
74VHC4066M
74VHC4066MTC
74VHC4066N
M14A
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Schematic Diagram
Top View
Truth Table
Input
CTL
L
Switch
I/O–O/I
“OFF”
“ON”
H
© 2000 Fairchild Semiconductor Corporation
DS011677
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Control Input Voltage (VIN
DC Switch I/O Voltage (VIO
Clamp Diode Current (IIK, IOK
)
−0.5 to +15V
−1.5 to VCC + 1.5V
EE − 0.5 to VCC + 0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
12
V
V
)
V
VCC
)
)
DC Output Current, per pin (IOUT
)
±25 mA
Operating Temperature Range (TA)
Input Rise or Fall Times (tr, tf)
−40
+85
°C
DC VCC or GND Current, per pin
(ICC
)
±50 mA
−65°C to +150°C
600 mW
V
V
V
CC = 2.0V
CC = 4.5V
CC = 9.0V
1000
500
ns
ns
ns
Storage Temperature Range (TSTG
Power Dissipation (PD) (Note 3)
S.O. Package only
)
400
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
Lead Temperature (TL)
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
(Soldering 10 seconds)
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
=25°C
T =−40 to 85°C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
2.0V
4.5V
9.0V
12.0V
4.5V
9.0V
12.0V
2.0V
4.5V
9.0V
12.0V
4.5V
9.0V
12.0V
1.5
3.15
6.3
8.4
0.5
1.35
2.7
3.6
170
85
1.5
3.15
5.3
8.4
0.5
1.35
2.7
3.6
200
105
85
V
V
IH
V
V
V
Maximum LOW Level
Input Voltage
V
IL
V
V
V
R
Maximum “ON” Resistance
See (Note 5)
V
V
= V , I = 2.0 mA
100
50
30
120
50
35
20
10
5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
µA
ON
CTL
IH
S
= V to GND
IS
CC
(Figure 1)
70
180
80
215
100
75
V
V
= V , I = 2.0 mA
IH S
CTL
= V or GND
60
IS
CC
(Figure 1)
40
60
R
Maximum “ON” Resistance
Matching
V
V
= V
IH
15
20
ON
CTL
= V to GND
10
15
IS
CC
5
10
15
I
Maximum Control
Input Current
V
V
V
V
V
V
V
V
V
= V or GND
±0.05
±0.5
IN
IN
CC
= 2 − 6V
CC
OS
I
Maximum Switch “OFF”
Leakage Current
= V or GND
6.0V
9.0V
10
15
20
10
15
20
±60
±80
±100
±40
±50
±60
1.0
±600
±800
±1000
±150
±200
±300
10
nA
nA
nA
nA
nA
nA
µA
µA
µA
IZ
CC
= GND or V
IS
CC
= V (Figure 2)
12.0V
6.0V
CTL
IL
I
Maximum Switch “ON”
Leakage Current
= V to GND
CC
IZ
IS
= V
9.0V
CTL
IH
= OPEN (Figure 3)
12.0V
6.0V
OS
I
Maximum Quiescent
Supply Current
= V or GND
CC
CC
IN
I
= 0 µA
9.0V
2.0
20
OUT
12.0V
4.0
40
Note 4: For a power supply of 5V ± 10% the worst case on resistance (R ) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing
ON
with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current occurs
IH
IL
CC
IH
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (V – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
CC
these devices be used to transmit digital only when using these supply voltages.
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2
AC Electrical Characteristics
V
CC = 2.0V−6.0V VEE = 0V−12V, C = 50 pF (unless otherwise specified)
L
T
=25°C
T =−40 to 85°C
A
A
V
Symbol
, t
Parameter
Conditions
Units
CC
Typ
25
5
Guaranteed Limits
t
Maximum Propagation
Delay Switch In to Out
3.3V
4.5V
9.0V
12.0V
3.3V
4.5V
9.0V
12.0V
3.3V
4.5V
9.0V
12.0V
4.5V
9.0V
30
10
8
20
13
10
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
4
3
7
t
, t
Maximum Switch Turn
R
R
R
= 1 kΩ
30
12
6
58
20
12
10
100
36
32
30
73
25
15
13
125
45
40
38
PZL PZH
L
“ON” Delay
5
t
, t
Maximum Switch Turn
“OFF” Delay
= 1 kΩ
60
25
20
15
40
100
PHZ PLZ
L
Minimum Frequency
= 600Ω
MHz
MHz
L
Response (Figure 7)
V
= 2 V at (V /2)
IS
PP
CC
20 log(V /V ) = −3 dB
(Note 6)(Note 7)
R = 600Ω, F = 1 MHz
L
O
I
Crosstalk Between
any Two Switches
(Figure 8)
(Note 7)(Note 8)
4.5V
9.0V
4.5V
9.0V
−52
−50
100
250
dB
dB
Peak Control to Switch
Feedthrough Noise
(Figure 9)
R
C
= 600Ω, F = 1 MHz
= 50 pF
mV
mV
L
L
Switch OFF Signal
Feedthrough
R
= 600Ω, F = 1 MHz
L
V
V
(CT) IL
Isolation
(Note 7)(Note 8)
4.5V
9.0V
−42
−44
dB
dB
(Figure 10)
THD
Total Harmonic
Distortion
R = 10 kΩ, C = 50 pF,
L L
F = 1 kHz
(Figure 11)
V
V
= 4 V
= 8 V
4.5V
9.0V
.013
.008
5
%
%
IS
IS
PP
PP
C
C
C
C
Maximum Control
Input Capacitance
Maximum Switch
Input Capacitance
Maximum Feedthrough
Capacitance
10
10
pF
IN
IN
IN
PD
20
0.5
15
pF
pF
pF
V
= GND
CTL
Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for F = 1 kHz (Null R /R
Attenuation).
ON
L
Note 7: V is centered at V /2.
IS
CC
Note 8: Adjust input for 0 dBm.
3
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AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
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4
AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
5
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Crosstalk and Distortion Test Circuits (Continued)
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical “ON” Resistance
Typical Crosstalk Between
Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid draw-
ing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not
exceed 0.6V (calculated from the ON resistance).
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6
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
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user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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