74VHC595M [FAIRCHILD]
8-Bit Shift Register with Output Latches; 具有输出锁存的8位移位寄存器
| 型号： | 74VHC595M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Shift Register with Output Latches |
| 文件： | 总9页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
Revised April 1999
74VHC595
8-Bit Shift Register with Output Latches
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
General Description
The VHC595 is an advanced high-speed CMOS Shift Reg-
ister fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has eight 3-STATE outputs. Separate clocks
are provided for both the shift register and the storage reg-
ister. The shift register has a direct-overriding clear, serial
input, and serial output (standard) pins for cascading. Both
the shift register and storage register use positive-edge
triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
Features
■ High Speed: tPD = 5.4 ns (typ) at VCC = 5V
■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: VOLP = 0.9V (typ)
■ Pin and function compatible with 74HC595
Ordering Code:
Order Number Package Number
Package Description
74VHC595M
74VHC595SJ
74VHC595MTC
74VHC595N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS011640.prf
www.fairchildsemi.com
Pin Descriptions
Truth Table
Pin Names
Description
Serial Data Input
Inputs
Function
H QA thru QH 3-STATE
SER
SCK
SER RCK SCK SCLR G
Shift Register Clock Input
(Active rising edge)
X
X
X
X
X
X
X
X
X
X
X
L
L
L
QA thru QH outputs enabled
Shift Register cleared
Q′H = 0
RCK
Storage Register Clock Input
(Active rising edge)
SCLR
G
Reset Input
L
H
X
X
X
↑
↑
↑
H
H
H
L
L
L
Shift Register clocked
3-STATE Output Enable Input
(Active LOW)
Q
N = Qn-1, Q0 = SER = L
Shift Register clocked
N = Qn-1, Q0 = SER = H
QA - QH
Parallel Data Outputs
Q’H
Serial Data Output
Q
X
Contents of Shift
Register transferred to
output latches
Timing Diagram
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2
Logic Diagram
(positive logic)
3
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to +5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±75 mA
V
V
CC = 3.3V ±0.3V
CC = 5.0V ±0.5V
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level
2.0
1.50
IH
V
V
Input Voltage
LOW Level
3.0 − 5.5 0.7 V
2.0
CC
CC
0.50
0.50
IL
Input Voltage
HIGH Level
Output Voltage
3.0 − 5.5
0.3 V
0.3 V
CC
CC
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V
I
= −50 µA
OH
IN
IH
OH
2.9
4.4
V
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
OL
V
LOW Level
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V
IN
OL
IH
Output Voltage
or V
IL
0.1
0.1
0.36
0.36
±0.25
0.44
0.44
±2.5
I
I
= 4 mA
= 8 mA
OL
OL
I
3-STATE
V
V
V
= V or GND
CC
OZ
IN
Output
= V or GND
CC
OUT
µA
Off-State
G = V or V
IH IL
IN
Current
I
I
Input Leakage Current
Quiescent Supply Current
0 − 5.5
±0.1
±1.0
µA
µA
V
V
= 5.5V or GND
IN
IN
5.5
4.0
40.0
= V or GND
CC
CC
IN
Noise Characteristics
T
= 25°C
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum
5.0
0.9
1.2
−1.2
3.5
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
L
L
L
L
V
V
V
V
(Note 3)
Dynamic V
OL
V
Quiet Output Minimum
Dynamic V
5.0
5.0
5.0
−0.9
OLV
(Note 3)
OL
V
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
IHD
(Note 3)
V
1.5
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
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4
AC Electrical Characteristics
T
= +25°C
T = −40°C to +85°C
A
V
A
CC
Symbol
Parameter
Units
ns
Conditions
(V)
Propagation Delay Time 3.3 ± 0.3
RCK to Q –Q
Min
Typ
7.7
Max
11.9
15.4
7.4
Min
Max
13.5
17.0
8.5
t
t
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
PLH
L
L
L
L
L
L
L
L
L
L
10.2
5.4
PHL
A
H
5.0 ± 0.5
ns
6.9
9.4
10.5
15.0
18.5
9.4
t
t
Propagation Delay Time 3.3 ± 0.3
8.8
13.0
16.5
8.2
PLH
PHL
ns
SCK–Q'H
11.3
6.2
5.0 ± 0.5
ns
7.7
10.2
12.8
16.3
11.4
13.7
17.2
t
Propagation Delay Time 3.3 ± 0.3
8.4
PHL
ns
10.9
SCLR –Q'H
5.0 ± 0.5
5.9
7.4
7.5
9.0
4.8
8.3
12.1
7.6
8.0
10.0
11.5
15.0
8.6
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
9.1
C
C
C
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
L
L
ns
11.1
13.5
17.0
10.0
12.0
16.2
11.0
t
t
Output Enable Time
G to Q –Q
3.3 ± 0.3
5.0 ± 0.5
R
R
= 1 kΩ
= 1 kΩ
PZL
PZH
L
ns
A
H
ns
10.6
15.7
10.3
t
t
f
Output Disable Time
G to Q –Q
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
PLZ
PHZ
MAX
L
ns
A
H
Maximum Clock
Frequency
80
55
150
130
185
155
70
50
C
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
MHz
MHz
ns
5.0 ± 0.5
135
95
115
85
t
t
Output to Output
Skew
3.3 ± 0.3
5.0 ± 0.5
1.5
1.0
10
1.5
1.0
10
(Note 4)
OSLH
OSHL
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
5.0
6.0
87
pF
pF
V
V
= Open
= 5.0V
IN
CC
OUT
PD
CC
(Note 5)
pF
Note 4: Parameter guaranteed by design. t
= | t
max − t
min|; t
= | t
max − t
min|.
PHL
OSLH
PLH
PLH
OSHL
PHL
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.) = C * V * f + I .
CC
CC
PD
CC
IN
5
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AC Operating Requirements
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Typ
Guaranteed Minimum
t
t
t
Minimum Setup Time
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.5
3.5
3.0
8.5
5.0
9.0
5.0
S
(SER–SCK)
3.0
8.0
5.0
8.0
5.0
Minimum Setup Time
(SCK–RCK)
S
S
ns
Minimum Setup Time
ns
(SCLR –RCK)
t
t
t
Minimum Hold Time
(SER–SCK)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
1.5
2.0
0.0
0.0
0.0
0.0
1.5
2.0
0.0
0.0
0.0
0.0
H
H
H
ns
Minimum Hold Time
(SCK–RCK)
ns
Minimum Hold Time
ns
(SCLR –RCK)
t
Minimum Pulse Width
3.3 ± 0.3
5.0 ± 0.5
5.0
5.0
5.0
5.0
W(L)
ns
ns
ns
ns
(SCLR)
t
t
t
t
t
Minimum Pulse Width
(SCK)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
5.0
5.0
5.0
5.0
3.0
2.5
5.0
5.0
5.0
5.0
3.0
2.5
W(L)
W(H)
W(L)
Minimum Pulse Width
(RCK)
(H)
W
Minimum Removal Time
rem
(SCLR –SCK)
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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