74VHC74MX [FAIRCHILD]
D Flip-Flop, AHC/VHC/H/U/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 0.150 INCH, LEAD FREE, MS-012AB, SOIC-14;
| 型号： | 74VHC74MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | D Flip-Flop, AHC/VHC/H/U/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 0.150 INCH, LEAD FREE, MS-012AB, SOIC-14 光电二极管 |
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1992
Revised March 1999
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
General Description
The VHC74 is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D input is
transferred to the Q output during the positive going transi-
tion of the CK pulse. CLR and PR are independent of the
CK and are accomplished by setting the appropriate input
LOW.
Features
■ High Speed: fMAX = 170 MHz (typ) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
■ Pin and function compatible with 74HC74
Ordering Code:
Order Number Package Number
Package Description
74VHC74M
74VHC74SJ
74VHC74MTC
74VHC74N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
Inputs
CLR PR
Outputs
Pin Names
D1, D2
Description
Data Inputs
Function
D
CK
X
Q
L
Q
H
L
L
H
L
H
L
X
X
X
L
Clear
CK1, CK2
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Output
X
H
Preset
CLR1, CLR2
PR1, PR2
L
X
H (Note 1) H (Note 1)
H
H
H
H
H
H
L
H
H
L
Q1, Q1, Q2, Q2
H
X
Qn
Qn
No Change
Note 1: This configuration is nonstable; that is, it will not persist when pre-
set and clear inputs return to their inactive (HIGH) state.
© 1999 Fairchild Semiconductor Corporation
DS011505.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to 5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±50 mA
V
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
Soldering (10 seconds)
)
−65°C to +150°C
0 20 ns/V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level Input
Voltage
2.0
1.50
IH
V
V
3.0 − 5.5 0.7 V
2.0
CC
CC
LOW Level Input
Voltage
0.50
0.50
IL
3.0 − 5.5
0.3 V
0.3 V
CC
CC
HIGH Level Output
Voltage
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V I = −50 µA
IH OH
OH
IN
2.9
4.4
V
V
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
4.5
V
LOW Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V I
IH OL
OL
IN
3.0
or V
IL
4.5
0.1
0.1
3.0
0.36
0.36
±0.1
2.0
0.44
0.44
±1.0
20.0
I
I
= 4 mA
= 8 mA
OL
OL
4.5
I
I
Input Leakage Current
0 − 5.5
5.5
µA
µA
V
V
= 5.5V or GND
IN
CC
IN
Quiescent Supply Current
= V or GND
CC
IN
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2
AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
MHz
MHz
ns
Conditions
Min
80
Typ
125
75
Max
Min
Max
f
Maximum Clock
3.3 ± 0.3
70
45
C
C
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
MAX
L
L
L
L
L
L
Frequency
50
5.0 ± 0.5
3.3 ± 0.3
130
90
170
115
6.7
9.2
110
75
t
t
Propagation Delay
Time (CK-Q, Q)
11.9
15.4
1.0
1.0
14.0
17.5
PLH
PHL
5.0 ± 0.5
3.3 ± 0.3
4.6
6.1
7.3
9.3
1.0
1.0
1.0
1.0
8.5
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
L
L
L
L
ns
10.5
14.5
18.0
t
t
Propagation Delay Time
(CLR, PR -Q, Q)
7.6
12.3
15.8
PLH
PHL
ns
10.1
5.0 ± 0.5
4.8
6.3
4
7.7
9.7
10
1.0
1.0
9.0
11.0
10
C
C
= 15 pF
= 50 pF
L
ns
L
C
C
Input Capacitance
Power Dissipation
Capacitance
pF
pF
V
= Open
CC
IN
25
(Note 4)
PD
Note 4: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained from the equation: I (opr.) = C * V * f + I /2 (per F/F).
CC
PD
CC
IN
CC
AC Operating Requirements
V
T
= 25°C
T = −40°C to +85°C
A
CC
A
Symbol
Parameter
Minimum Pulse Width (CK)
Units
(V)
(Note 5)
Typ
Guaranteed Minimum
t
t
t
(L)
(H)
(L)
3.3
6.0
7.0
5.0
7.0
W
W
W
ns
ns
ns
ns
ns
5.0
5.0
6.0
3.3
Minimum Pulse Width (CLR, PR)
Minimum Setup Time
5.0
3.3
5.0
3.3
5.0
3.3
5.0
6.0
5.0
0.5
0.5
5.0
5.0
7.0
5.0
0.5
0.5
5.0
t
t
t
S
H
Minimum Hold Time
Minimum Recovery Time (CLR, PR)
REC
5.0
3.0
3.0
Note 5: V is 3.3 ± 0.3V or 5.0 ± 0.5V
CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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