74VHC86MTCX_NL [FAIRCHILD]
Quad 2-Input Exclusive-OR Gate; 四2输入异或门
| 型号： | 74VHC86MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input Exclusive-OR Gate |
| 文件： | 总7页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1992
Revised February 2005
74VHC86
Quad 2-Input Exclusive-OR Gate
General Description
Features
The VHC86 is an advanced high speed CMOS Quad
Exclusive OR Gate fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
■ High Speed: tPD 4.8 ns (typ) at VCC 5V
■ Low Power Dissipation: ICC A (Max.) @ TA 25 C
2
■ High Noise Immunity: VNIH VNIL 28% VCC (Min.)
■ Power down protection is provided on all inputs
■ Low Noise: VOLP 0.8V (Max.)
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and on two supply systems such as battery back up. This
circuit prevents device destruction due to mismatched sup-
ply and input voltages.
■ Pin and Function Compatible with 74HC86
Ordering Code:
Package
Order Number
Package Description
Number
74VHC86M
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC86SJ
74VHC86MTC
MTC14
MTC14
74VHC86MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC86N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
A
L
B
L
O
L
Pin Names
A0–A3
Description
Inputs
L
H
L
H
H
L
H
H
B0–B3
Inputs
H
O0–O3
Outputs
© 2005 Fairchild Semiconductor Corporation
DS011517
www.fairchildsemi.com
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
)
2.0V to 5.5V
0V to 5.5V
0V to VCC
)
)
)
)
)
20 mA
)
40 C to 85 C
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 3.3V 0.3V
)
50 mA
0 ns/V 100 ns/V
0 ns/V 20 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
VCC 5.0V 0.5V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260 C
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
Max
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Max
Min
1.50
0.7 V
V
V
V
HIGH Level
2.0
1.50
IH
V
V
Input Voltage
LOW Level
3.0 5.5 0.7 V
2.0
CC
CC
0.50
0.50
0.3 V
IL
Input Voltage
HIGH Level
Output Voltage
3.0 5.5
0.3 V
CC
CC
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
V I
IH OH
50 A
OH
IN
2.9
4.4
V
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
4 mA
8 mA
OH
OH
V
LOW Level
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V I
IH OL
50 A
OL
IN
Output Voltage
or V
IL
0.1
0.1
0.36
0.36
0.1
0.44
0.44
1.0
I
I
4 mA
8 mA
OL
OL
I
I
Input Leakage Current
0
5.5
5.5
A
A
V
V
5.5V or GND
V or GND
CC
IN
CC
IN
Quiescent Supply Current
2.0
20.0
IN
Noise Characteristics
T
25 C
V
(V)
A
CC
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
Conditions
Typ
Limit
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
(Note 4)
OL
L
L
L
L
5.0
5.0
5.0
5.0
0.3
0.8
V
V
V
V
V
Quiet Output Minimum Dynamic V
OL
OLV
(Note 4)
0.3
0.8
3.5
1.5
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
(Note 4)
V
ILD
(Note 4)
Note 4: Parameter guaranteed by design.
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2
AC Electrical Characteristics
T
25 C
Typ
T
A
40 C to 85 C
V
(V)
A
CC
Symbol
Parameter
Propagation Delay
Units
ns
Conditions
Min
Max
11.0
14.5
6.8
Min
Max
13.0
16.5
8.0
t
t
3.3 0.3
7.0
9.5
4.8
6.3
4
1.0
1.0
1.0
1.0
C
C
C
C
15 pF
50 pF
15 pF
50 pF
PHL
PLH
L
L
5.0 0.5
L
ns
8.8
10.0
10
L
C
C
Input Capacitance
10
pF
pF
V
Open
IN
CC
Power Dissipation Capacitance
18
(Note 5)
PD
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.)
C
* V * f
I
/4 (per gate).
CC
CC
PD
CC
IN
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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