74VHCT541AM [FAIRCHILD]
Octal Buffer/Line Driver with 3-STATE Outputs; 八路缓冲器/ 3态输出线路驱动器
| 型号： | 74VHCT541AM |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal Buffer/Line Driver with 3-STATE Outputs |
| 文件： | 总7页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1997
Revised April 2005
74VHCT541A
Octal Buffer/Line Driver with 3-STATE Outputs
Protection circuits ensure that 0V to 7V can be applied to
General Description
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
The VHCT541A is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
Note 1: Outputs in OFF-state.
The VHCT541A is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
Features
■ High Speed: tPD 5.5 ns (typ) at VCC 5V
This device is similar in function to the VHCT244A while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
■ Low power dissipation: ICC
4 A (max) at TA 25 C
■ Power down protection is provided on all inputs and
outputs
■ Pin and function compatible with 74HCT541
Ordering Code:
Order Number Package Number
Package Description
74VHCT541AM
74VHCT541ASJ
74VHCT541AMTC
74VHCT541AN
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Inputs
Outputs
Pin Descriptions
OE1
OE2
I
Pin Names Description
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
OE1, OE2
I0 - I7
3-STATE Output Enable Inputs
Inputs
O0 - O7
3-STATE Outputs
H
X
HIGH Voltage Level
Immaterial
L
Z
LOW Voltage Level
High Impedance
© 2005 Fairchild Semiconductor Corporation
DS500013
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Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to 5.5V
DC Output Voltage (VOUT
)
Input Voltage (VIN
)
(Note 3)
0.5V to 7.0V
0.5V to V CC + 0.5V
20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 4)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
)
(Note 3)
Output Diode Current (IOK
(Note 5)
)
Operating Temperature (TOPR
)
40 C to 85 C
20 mA
25 mA
Input Rise and Fall Time (tr, tf)
VCC 5.0V 0.5V
DC Output Current (IOUT
)
0
20 ns/V
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
DC VCC/GND Current (ICC
)
75 mA
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
260 C
Note 3: When Outputs are in OFF-State OR when V
0V.
CC
Note 4: HIGH or LOW state
I
absolute maximum rating must be
OUT
observed.
Note 5: V
GND,.V
V
(Outputs Active).
OUT
OUT
CC
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
Min Max
V
(V)
A
A
CC
Symbol
Parameter
Units
Conditions
Min
Max
V
V
V
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
4.5 5.5
4.5 5.5
4.5
2.0
2.0
V
V
V
V
V
V
A
IH
0.8
0.8
IL
4.4
4.5
0.0
4.4
V
V
V
V
V
I
I
I
I
50
8 mA
50
8 mA
A
OH
IN
IH
OH
OH
OL
OL
4.5
3.94
3.80
V
LOW Level Output Voltage
4.5
0.1
0.1
0.44
2.5
A
OL
IN
IL
4.5
0.36
0.25
I
3-STATE Output
5.5
V
V
V
V
V
or V
IL
OZ
IN
IH
V
Off-State Current
or GND
CC
OUT
IN
I
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
0.1
4.0
1.0
40.0
1.50
A
A
5.5V or GND
V or GND
CC
IN
I
CC
IN
I
Maximum I /Input
CC
5.5
1.35
mA
3.4V
CCT
IN
Other Inputs
V
or GND
CC
I
Output Leakage Current
0
0.5
5.0
A
V
OUT
5.5V
OFF
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2
Noise Characteristics
T
25 C
Limits
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Typ
V
Quiet Output Maximum Dynamic V
5.0
1.2
1.6
1.6
2.0
0.8
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
OL
L
L
L
L
(Note 7)
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
1.2
V
V
V
OLV
OL
(Note 7)
V
Minimum HIGH Level Dynamic Input Voltage
Maximum HIGH Level Dynamic Input Voltage
IHD
(Note 7)
V
ILD
(Note 7)
Note 7: Parameter guaranteed by design.
AC Electrical Characteristics
T
25 C
Typ
T
40 C to 85 C
V
(V)
A
A
CC
Symbol
Parameter
Units
Conditions
Min
Max
6.9
Min
Max
8.0
t
t
t
t
t
t
t
t
Propagation Delay
5.0 0.5
5.0
5.5
8.3
8.8
9.4
1.0
1.0
1.0
1.0
1.0
ns
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
50 pF
PLH
L
L
L
L
L
Time
7.9
9.0
PHL
3-STATE Output
Enable Time
5.0 0.5
5.0 0.5
5.0 0.5
11.3
12.3
11.9
13.0
14.0
13.5
ns
ns
ns
R
1 k
1 k
PZL
L
PZH
PLZ
3-STATE Output
Disable Time
Output to Output Skew
R
L
PHZ
OSLH
OSHL
1.0
10
1.0
10
(Note 8)
C
50 pF
L
C
C
C
Input Capacitance
4
9
pF
pF
V
Open
5.0V
IN
CC
CC
Output Capacitance
V
OUT
PD
Power Dissipation Capacitance
19
pF (Note 9)
Note 8: Parameter guaranteed by design. t
|t
t
|; t
|t
t
|.
PHLmin
OSLH
PLHmax
PLHmin OSHL
PHLmax
Note 9: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (OPR.)
C
* V * f
I
/8 (per bit).
CC
PD
CC
IN
CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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相关型号：
74VHCT541AMTCX_NL
Bus Driver, AHCT/VHCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153AC, TSSOP-20
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