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数据手册74VHCT74MTC 概述
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74VHCT74MTC 数据手册
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PDF下载July 1997
Revised February 2005
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
Features
The VHCT74A is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D INPUT is transferred to the Q OUTPUT during the
positive going transition of the CK pulse. CLR and PR are
independent of the CK and are accomplished by setting the
appropriate input LOW.
■ High speed: fMAX 160 MHz (typ) at TA 25 C
■ High noise immunity: VIH 2.0V, VIL 0.8V
■ Power down protection is provided on all inputs and
outputs
■ Low power dissipation:
ICC
2 A (max) at TA 25 C
■ Pin and function compatible with 74HCT74
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with VCC
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Ordering Code:
Package
Order Number
Package Description
Number
74VHCT74AM
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHCT74AMX_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHCT74ASJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT74AMTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT74AMTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1)
Wide
74VHCT74AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS500026
www.fairchildsemi.com
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Table
Pin Descriptions
Inputs
CLR PR
Outputs
Pin Names
D1, D2
Description
Data Inputs
Function
D
CK
X
Q
L
Q
H
L
L
H
L
H
L
X
X
X
L
Clear
CK1, CK2
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
X
H
H
L
Preset
CLR1, CLR2
PR1, PR2
L
X
H
H
L
H
H
H
H
H
H
H
X
H
Qn
Q1, Q1, Q2, Q2
Qn No
Change
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 6)
Supply Voltage (VCC
)
0.5V to 7.0V
0.5V to 7.0V
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to 5.5V
DC Output Voltage (VOUT
)
Input Voltage (VIN
)
(Note 3)
0.5V to VCC 0.5V
0.5V to 7.0V
20 mA
Output Voltage (VOUT
)
(Note 4)
(Note 3)
0V to VCC
0V to 5.5V
Input Diode Current (IIK
)
(Note 4)
Output Diode Current (IOK
(Note 5)
)
Operating Temperature (TOPR
)
40 C to 85 C
20 mA
25 mA
Input Rise and Fall Time (tr, tf)
VCC 5.0V 0.5V
DC Output Current (IOUT
)
0 ns/V 20 ns/V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
DC VCC/GND Current (ICC
)
50 mA
Storage Temperature (TSTG
Lead Temperature (TL)
Soldering (10 seconds)
)
65 C to 150 C
260 C
Note 3: HIGH or LOW state.
I
absolute maximum rating must be
OUT
observed.
Note 4: V
0V.
GND, V
CC
Note 5: V
V
.(Outputs Active)
OUT
OUT
CC
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
25 C
Typ
T
40 C to 85 C
Min Max
CC
A
A
Symbol
Parameter
Units
Conditions
(V)
4.5
Min
2.0
2.0
Max
V
V
V
V
HIGH Level
2.0
2.0
IH
V
V
V
V
Input Voltage
5.5
LOW Level
4.5
0.8
0.8
0.8
0.8
IL
Input Voltage
5.5
HIGH Level
4.5
4.40
3.94
4.50
0.0
4.40
3.80
V
V
V
I
OH
50
A
OH
OL
IN
IH
Output Voltage
LOW Level
4.5
or V
I
8 mA
IL OH
4.5
0.1
0.36
0.1
0.1
0.44
1.0
V
I
50
A
IN
IH
OL
Output Voltage
Input Leakage Current
Quiescent Supply Current
4.5
or V
I
8 mA
5.5V or GND
V or GND
CC
IL OL
I
I
I
0–5.5
5.5
A
A
V
V
V
IN
IN
IN
IN
2.0
20.0
CC
Maximum I /Input
CC
3.4V
CCT
5.5
0.0
1.35
0.5
1.50
5.0
mA
A
Other Inputs
V 5.5V
OUT
V
or GND
CC
I
Output Leakage Current
(Power Down State)
OFF
3
www.fairchildsemi.com
AC Electrical Characteristics
V
(V)
(Note 7)
T
25 C
Typ
T
40 C to 85 C
Min Max
CC
A
A
Symbol
Parameter
Units
Conditions
Min
Max
f
Maximum Clock
5.0
5.0
5.0
5.0
5.0
5.0
100
80
160
140
5.8
6.3
7.6
8.1
4
80
65
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
Open
MAX
L
MHz
ns
Frequency
L
t
t
t
t
Propagation Delay Time
(CK-Q, Q)
7.8
8.8
1.0
1.0
1.0
1.0
9.0
10.0
12.0
13.0
10
PLH
PHL
PLH
PHL
L
L
Propagation Delay time
(CLR, PR -Q, Q)
10.4
11.4
10
L
ns
L
C
C
Input Capacitance
Power Dissipation Capacitance
pF
pF
V
CC
IN
24
(Note 8)
PD
Note 7: V is 5.0 0.5V
CC
Note 8: C
is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr)
CC
C
V
f
I
/2 (per flip-flop).
PD
CC
IN
CC
AC Operating Requirements
V
T
25 C
T
40 C to 85 C
Guaranteed Minimum
CC
A
A
Symbol
Parameter
Minimum Pulse Width (CK)
Units
ns
(V)
Typ
t
(L)
(H)
(L)
W
5.0 0.5
5.0 0.5
5.0
5.0
5.0
t
W
t
Minimum Pulse Width
(CLR, PR)
W
5.0
ns
t
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time
(CLR, PR)
5.0 0.5
5.0 0.5
5.0 0.5
5.0
0
5.0
0
ns
ns
ns
S
t
H
t
3.5
3.5
REM
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
8
74VHCT74MTC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 74VHCT74MX | ETC | Dual D-Type Flip-Flop | 获取价格 |
|
| 74VHCT74N | FAIRCHILD | D Flip-Flop, AHCT/VHCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDIP14, PLASTIC, DIP-14 | 获取价格 |
|
| 74VHCT74N | TI | AHCT/VHCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, 0.300 INCH, PLASTIC, DIP-14 | 获取价格 |
|
| 74VHCT74SJ | FAIRCHILD | D Flip-Flop, AHCT/VHCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, EIAJ, PLASTIC, SOIC-14 | 获取价格 |
|
| 74VHCT74SJX | ETC | Dual D-Type Flip-Flop | 获取价格 |
|
| 74VHCT86 | STMICROELECTRONICS | QUAD EXCLUSIVE OR GATE | 获取价格 |
|
| 74VHCT86A | STMICROELECTRONICS | QUAD EXCLUSIVE OR GATE | 获取价格 |
|
| 74VHCT86AM | STMICROELECTRONICS | QUAD EXCLUSIVE OR GATE | 获取价格 |
|
| 74VHCT86AMTR | STMICROELECTRONICS | AHCT/VHCT SERIES, QUAD 2-INPUT XOR GATE, PDSO14, SO-14 | 获取价格 |
|
| 74VHCT86AT | STMICROELECTRONICS | QUAD EXCLUSIVE OR GATE | 获取价格 |
|
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