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ACE8000 [FAIRCHILD]

ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications; ACE8001产品系列算术控制器引擎（ ACEX ™ ）针对低功耗应用
ACE8000
型号： ACE8000
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
ACE8001产品系列算术控制器引擎（ ACEX ™ ）针对低功耗应用

控制器
文件： 总31页 (文件大小：204K)
中文：  中文翻译
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November 2002  
ACE8001 Product Family  
Arithmetic Controller Engine (ACEx™)  
for Low Power Applications  
  Multi-input wake-up 3 I/O pins  
General Description  
  8-bit Timer1 with PWM output  
The ACE8001 is a member of the ACEx (Arithmetic Controller  
Engine) family of microcontrollers. It is a dedicated programma-  
ble monolithic integrated circuit for applications requiring high  
performance, low power, and small size. It is a fully static part  
fabricated using CMOS technology.  
  On-chip oscillator  
— No external components  
— 1µs instruction cycle time  
  On-chip Power-on Reset  
— External Reset pin option (ACE8000)  
The ACE8001 product family has an 8-bit core processor, 64  
bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code  
EEPROM. Its on-chip peripherals include a programmable 8-bit  
timer with PWM output, watch-dog/idle timer, and programma-  
ble undervoltage detection circuitry. The on-chip clock and reset  
functions reduce the number of required external components.  
The ACE8001 product family is available in 8-pin SOIC and  
TSSOP packages.  
  Brown-out Reset  
  Programmable read and write disable functions  
  Memory mapped I/O  
  Multilevel Low Voltage Detection  
  Fully static CMOS  
— Low power HALT mode (100nA @ 3.3V)  
— Power saving IDLE mode  
  Single supply operaton  
Features  
— 2.2 - 5.5V  
  Arithmetic Controller Engine  
  1K bytes on-board code EEPROM  
  64 bytes data EEPROM  
  Fast Startup (<10µS)  
  64 bytes RAM  
  Software selectable I/O options  
— Push-pull outputs with tri-state option  
— Weak pull-up or high impedance inputs  
  40 years data retention  
  1,000,000 writes  
  8-pin SOIC and TSSOP packages.  
  Watchdog  
Block and Connection Diagram  
VCC1  
GND1  
Power-on Reset  
Brown-out Reset  
RESET  
HALT & IDLE Power  
Saving Modes  
Internal Oscillator  
ACE1001 core  
(CKO) G0  
GPORT  
12-bit Timer0 with  
Watchdog Timer  
(CKI) G1  
general  
purpose  
I/O with  
multi-  
input  
wakeup  
on 3  
inputs  
(4 interrupt  
sources  
and vectors)  
(T1) G2  
8-bit PWM Timer1  
(MIW) G32  
64 bytes of Data  
EEPROM  
Programming Interface  
(MIW) G4  
(MIW) G5  
1K bytes of Code  
EEPROM  
64 bytes of RAM  
1. 100nf decoupling capacitor recommended.  
2. Input only  
©2002 Fairchild Semiconductor Corporation  
ACE8001 Product Family Rev. B.2  
1
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Figure 1: ACE8001 SOIC 8-Pin Device Pinout  
(a) Normal Operation  
(b) Programming Mode  
1
2
3
4
8
7
6
5
1
8
7
6
5
(MIW) G3  
(MIW) G4  
(MIW) G5  
(CKO) G0  
VCC  
LOAD  
VCC  
2
GND  
SFT_IN  
GND  
3
G2 (T1)  
G1 (CKI)  
NC/VCC  
SFT_OUT  
CKI  
4
NC  
Figure 2: ACE8000 SOIC 8-Pin Reset Option  
(a) Normal Operation  
(b) Programming Mode  
1
2
3
4
8
7
6
5
1
8
(MIW) G3  
(MIW) G4  
Reset  
VCC  
LOAD  
VCC  
2
7
6
5
GND  
SFT_IN  
GND  
3
G2 (T1)  
G1 (CKI)  
NC  
SFT_OUT  
CKI  
4
(CKO) G0  
NC  
Figure 3: ACE8001 TSSOP 8-Pin Device Pinout  
(a) Normal Operation  
(b) Programming Mode  
1
2
3
4
8
7
6
5
1
8
7
6
5
VCC  
(MIW) G3  
(MIW) G5  
(MIW) G4  
G2 (T1)  
GND  
VCC  
SFT_OUT  
GND  
2
LOAD  
3
G1 (CKI)  
G0 (CKO)  
NC/VCC  
CKI  
4
SFT_IN  
NC  
2
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ACE8001 Product Family Rev. B.2  
2.0 Electrical Characteristics  
Absolute Maximum Ratings  
Operating Conditions  
Ambient Storage Temperature  
-65˚C to +150˚C  
Relative Humidity (non-condensing)  
EEPROM write limits  
95%  
Input Voltage not including G3  
G3 Input Voltage  
-0.3V to V +0.3V  
See DC Electrical  
Characteristics  
CC  
0.3V to 13V  
+300˚C  
Lead Temperature (10s max)  
Electrostatic Discharge on all pins  
2000V min  
Device  
ACE8001  
ACE8001E  
ACE8000  
ACE8000E  
Operating Voltage  
Operating Temperature  
2.2 to 5.5V  
0°C to 70°C  
-40°C to +85°C  
0°C to 70°C  
2.2 to 5.5V  
2.2 to 5.5V  
2.2 to 5.5V  
-40°C to +85°C  
3
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
ACE8001 DC Electrical Characteristics  
V
= 2.2 to 5.5V  
CC  
All measurements valid for ambient operating temperature unless otherwise stated.  
Symbol  
Parameter  
Conditions  
MIN  
TYP  
MAX  
Units  
3
I
Supply Current –  
-40°C to +85°C  
CC  
no data EEPROM write in  
progress  
2.2V  
2.7V  
3.3V  
5.5V  
0.4  
0.7  
1.2  
3.7  
1.0  
1.2  
2.0  
6.0  
mA  
mA  
mA  
mA  
I
HALT Mode current  
3.3V @ -40°C to +85°C  
5.5V @ -40°C to +85°C  
100  
0.7  
5000  
25  
nA  
µA  
CCH  
4
I
IDLE Mode Current  
3.3V  
5.5V  
120  
140  
200  
350  
µA  
µA  
CCL  
V
EEPROM Write Voltage  
Code EEPROM in  
Programming Mode  
4.5  
2.4  
5.0  
5.5  
V
CCW  
Data EEPROM in  
Operating Mode  
5.5  
V
S
Power Supply Slope  
1µs/V  
10ms/V  
VCC  
V
Input Low with Schmitt  
Trigger Buffer  
V
= 2.2 -5.5V  
0.2V  
CC  
V
IL  
IH  
IP  
CC  
V
Input High with Schmitt  
Trigger Buffer  
V
V
= 2.2V  
> 2.2V  
0.9V  
0.8V  
V
V
CC  
CC  
CC  
CC  
I
Input Pull-up Current  
TRI-STATE Leakage  
Output Low Voltage  
G0, G1, G2, G4  
G5  
V
V
V
=5.5V, V =0V  
30  
65  
2
350  
200  
µA  
nA  
CC  
CC  
CC  
IN  
I
=5.5V  
TL  
V
= 2.2V – 3.3V  
OL  
3.0 mA sink  
5.0 mA sink  
0.2V  
0.2V  
V
V
CC  
CC  
Output Low Voltage  
G0, G1, G2, G4  
G5  
V
= 3.3V – 5.5V  
CC  
5.0 mA sink  
0.2V  
0.2V  
V
V
CC  
CC  
10.0 mA sink  
V
Output High Voltage  
G0, G1, G2, G4  
G5  
V
= 2.2V – 5.5V  
CC  
OH  
0.4 mA source  
0.8 mA source  
0.8V  
0.8V  
V
V
CC  
CC  
Output High Voltage  
G0, G1, G2, G4  
G5  
V
= 3.3V – 5.5V  
CC  
0.4 mA source  
1.0 mA source  
0.8V  
0.8V  
V
V
CC  
CC  
3
4
I
active current is dependent on the program code.  
CC  
Based on a continuous IDLE looping program.  
4
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ACE8001 Product Family Rev. B.2  
ACE8001 AC Electrical Characteristics  
V
= 2.2 to 5.5V  
CC  
All measurements valid for ambient operating temperature unless otherwise stated.  
Parameter  
Conditions  
MIN  
TYP  
MAX  
Units  
Instruction cycle time from  
internal clock - setpoint  
5.0V at +25°C  
0.96  
1.0  
1.04  
µs  
Internal clock frequency  
variation  
2.4V to 5.5V at  
constant temperature  
10  
+8  
%
%
2.4V to 5.5V at  
-12  
full temperature range  
Crystal oscillator frequency  
External clock frequency  
EEPROM write time  
(Note 5)  
(Note 5)  
4
4
MHz  
MHz  
ms  
2.5  
5
3
Internal clock start up time  
Oscillator start up time  
(Note 6)  
(Note 6)  
20  
µs  
cycles  
5
6
The maximum permissible frequency is guaranteed by design but not 100% tested.  
The parameter is guaranteed by design but not 100% tested.  
ACE8001 Electrical Characteristics for programming  
All data following is valid between 4.5V and 5.5V at ambient temperature. The following characteristics are  
guaranteed by design but are not 100% tested. See “EEPROM write time” in the AC Electrical Characteris-  
tics for definition of the programming ready time.  
Parameter  
Description  
MIN  
500  
500  
100  
100  
100  
900  
50  
MAX  
DC  
Units  
ns  
t
t
t
t
t
t
t
t
CLOCK high time  
HI  
CLOCK low time  
DC  
ns  
LO  
SHIFT_IN setup time  
SHIFT_IN hold time  
SHIFT_OUT setup time  
SHIFT_OUT hold time  
LOAD supervoltage timing  
LOAD timing  
ns  
DIS  
DIH  
DOS  
DOH  
ns  
ns  
ns  
, t  
µs  
SV1 SV2  
, t  
, t  
, t  
5
µs  
LOAD1 LOAD2 LOAD3 LOAD4  
V
Supervoltage level  
11.5  
12.5  
V
SUPERVOLTAGE  
ACE8001 Brown-out Reset (BOR) Characteristics  
V
= 2.2 to 5.5V  
CC  
Parameter  
Conditions  
MIN  
TYP  
MAX  
Units  
BOR Voltage Threshold  
Variation (BLSEL = 1)  
-40°C to +85°C  
2.25  
V
5
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ACE8001 Product Family Rev. B.2  
3.0 AC & DC Electrical Characteristic Graphs  
The graphs in this section are for design guidance and are based on preliminary test data.  
Figure 4: RC Oscillator Frequency vs.Temperature  
(a) VCC = 5.0V  
2.600  
2.400  
2.200  
2.000  
1.800  
1.600  
1.400  
1.200  
1.000  
Avg  
Min  
Max  
3.3k/82pF  
5.6k/100pF  
6.8K/100pF  
Resistor & Capacitor Values [k & pF]  
(b)VCC=2.5V  
1.600  
1.400  
1.200  
1.000  
0.800  
0.600  
Avg  
Min  
Max  
3.3k/82pF  
5.6k/100pF  
6.8K/100pF  
Resistor & Capacitor Values [k & pF]  
Figure 5: Internal Oscillator Frequency  
1.040  
1.020  
1.000  
0.980  
0.960  
0.940  
0.920  
0.900  
0.880  
2.4 V  
3.0 V  
3.3 V  
3.6 V  
4.0 V  
4.5 V  
5.0 V  
5.5 V  
-45C  
-20C  
0C  
25C  
85C  
125C  
Temperature (°C)  
6
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ACE8001 Product Family Rev. B.2  
Figure 6: LBD and BOR Threshold Levels  
LBD Voltage Levels vs. Temperature  
4.00  
3.80  
3.60  
3.40  
3.20  
3.00  
2.80  
2.60  
2.40  
2.20  
2.00  
Level 1  
Level 2  
Level 3  
Level 4  
Level 5  
Level 6  
Level 7  
Level 8  
-45C  
0C  
25C  
85C  
125C  
Temperature [
°
C]  
BOR Voltage Level vs. Temperature  
2.70  
2.60  
2.50  
2.40  
2.30  
2.20  
2.10  
2.00  
1.90  
BOR Level  
-45C  
0C  
25C  
85C  
125C  
Temperature [
°
C]  
7
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ACE8001 Product Family Rev. B.2  
Figure 7: I Active Current  
CC  
I
Active (no data EEPROM writes) vs. Temperature  
CC  
4.50  
4.00  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
2.2V  
2.7V  
3.3V  
5.0V  
5.5V  
-45  
0
25  
85  
125  
Temperature [
°
C]  
I
Active (data EEPROM writes) vs. Temperature  
CC  
12.00  
10.00  
8.00  
2.2V  
2.7V  
3.3V  
5.0V  
5.5V  
6.00  
4.00  
2.00  
0.00  
-45  
0
25  
85  
125  
Temperature [
°
C]  
8
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ACE8001 Product Family Rev. B.2  
Figure 8: HALT Mode Currents  
HALT current vs. Temperature  
12.000  
10.000  
8.000  
6.000  
4.000  
2.000  
5.5V  
5.0V  
3.3V  
0.000  
-45C  
0C  
25C  
85C  
125C  
Temperature [
°
C]  
Figure 9: IDLE Mode Current  
IDLE current vs. Temperature  
160.00  
140.00  
120.00  
100.00  
80.00  
2.2V  
2.7V  
3.3V  
5.0V  
5.5V  
60.00  
40.00  
20.00  
0.00  
-45  
0
25  
85  
125  
Temperature [
°
C]  
9
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ACE8001 Product Family Rev. B.2  
Figure 10:VOL/VOH  
VOL vs. IOL (G5 @ 25
°
C)  
VOL vs. IOL (G0-G4 @ 25
°
C)  
1.40  
1.20  
1.00  
0.80  
0.60  
0.40  
0.20  
0.00  
0.80  
0.70  
0.60  
0.50  
0.40  
0.30  
0.20  
0.10  
0.00  
2.2V  
2.7V  
2.2V  
2.7V  
3.3V  
3.6V  
5.5V  
0
2
5
8
15  
0
2
5
8
15  
Current (mA)  
Current (mA)  
VOH vs. IOH (G0-G4 @ 25
°
C)  
VOH vs. IOH (G5 @ 25
°
C)  
6.00  
5.50  
5.00  
4.50  
4.00  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
6.00  
5.50  
5.00  
4.50  
4.00  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
2.2V  
2.7V  
2.2V  
2.7V  
3.3V  
3.6V  
5.5V  
0
0.2  
0.4  
0.5  
0.8  
1
1.2  
0
0.2  
0.4  
0.5  
0.8  
1
1.2  
Current (mA)  
Current (mA)  
10  
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ACE8001 Product Family Rev. B.2  
either segment of the memory map. This modification improves  
the overall code efficiency of the core and takes advantage of  
the flexibility found on Von Neumann style machines.  
4.0 Arithmetic Controller Core  
The ACEx microcontroller core is specifically designed for low  
cost applications involving bit manipulation, shifting and arith-  
metic operations. It is based on a modified Harvard architecture  
meaning peripheral, I/O, and RAM locations are addressed sep-  
arately from instruction data.  
4.1 CPU Registers  
The ACEx microcontroller has five general-purpose registers.  
These registers are the Accumulator (A), X-Pointer (X), Pro-  
gram Counter (PC), Stack Pointer (SP), and Status Register  
(SR). The X, SP, and SR registers are all memory-mapped.  
The core differs from the traditional Harvard architecture by  
aligning the data and instruction memory sequentially. This  
allows the X-pointer (11-bits) to point to any memory location in  
Figure 11: Programming Model  
7
0
0
0
0
A
8-bit accumulator register  
11-bit X pointer register  
10-bit program counter  
4-bit stack pointer  
10  
9
X
PC  
SP  
SR  
3
8-bit status register  
R 0 0 G Z C H N  
NEGATIVE flag  
HALF CARRY flag (from bit 3)  
CARRY flag (from MSB)  
ZERO flag  
GLOBAL Interrupt Mask  
READY flag (from EEPROM)  
11  
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ACE8001 Product Family Rev. B.2  
The stack is configured as a data structure which decrements  
from high to low memory. Each time a new address is pushed  
onto the stack, the core decrements the stack pointer by two.  
Each time an address is pulled from the stack, the core incre-  
ments the stack pointer by two. At any given time, the stack  
pointer points to the next free location in the stack.  
4.1.1 Accumulator (A)  
The Accumulator is a general-purpose 8-bit register that is used  
to hold data and results of arithmetic calculations or data manip-  
ulations.  
4.1.2 X-Pointer (X)  
When a subroutine is called by a jump to subroutine (JSR)  
instruction, the address of the instruction is automatically  
pushed onto the stack least significant byte first. When the sub-  
routine is finished, a return from subroutine (RET) instruction is  
executed. The RET instruction pulls the previously stacked  
return address from the stack and loads it into the program  
counter. Execution then continues at the recovered return  
address.  
The X-Pointer register allows for an 11-bit indexing value to be  
added to an 8-bit offset creating an effective address used for  
reading and writing between the entire memory space. (Soft-  
ware can only read from code EEPROM.) This provides soft-  
ware with the flexibility of storing lookup tables in the code  
EEPROM memory space for the core’s accessibility during nor-  
mal operation.  
The X register is divided into two sections. The 10 least signifi-  
cant bits (LSB) of the register is the address of the program or  
data memory space. The most significant bit (MSB) of the regis-  
ter is write only and selects between the data (0x000 to 0x0FF)  
or program (0xC00 to 0xFFF) memory space.  
4.1.5 Status Register (SR)  
This 8-bit register contains four condition code indicators (C, H,  
Z, and N), an interrupt masking bit (G), and an EEPROM write  
flag (R). The condition code indicators are automatically  
updated by most instructions. (See Table 8)  
Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take  
a value from address range 0x000 to 0x0FF and load it into A. If  
Bit 10 = 1, then the LD A, [00,X] instruction will take a value  
from address range 0xC00 to 0xFFF and load it into A.  
Carry/Borrow (C)  
The carry flag is set if the arithmetic logic unit (ALU) performs a  
carry or borrow during an arithmetic operation and by its dedi-  
cated instructions. The rotate instruction operates with and  
through the carry bit to facilitate multiple-word shift operations.  
The LDC and INVC instructions facilitate direct bit manipulation  
using the carry flag.  
4.1.3 Program Counter (PC)  
The 10-bit program counter register contains the address of the  
next instruction to be executed. After a reset, if in normal mode  
the program counter is initialized to 0xC00.  
Half Carry (H)  
4.1.4 Stack Pointer (SP)  
The half carry flag indicates whether an overflow has taken  
place on the boundary between the two nibbles in the accumu-  
lator. It is primarily used for Binary Coded Decimal (BCD) arith-  
metic calculation.  
The ACEx microcontroller has an automatic program stack with  
a 4-bit stack pointer. The stack can be initialized to any location  
between addresses 0x30-0x3F. After a reset, the stack pointer  
is defaulted to 0xF pointing to address 0x3F. Normally, the stack  
pointer is initialized by one of the first instructions in an applica-  
tion program.  
Zero (Z)  
The zero flag is set if the result of an arithmetic, logic, or data  
manipulation operation is zero. Otherwise, it is cleared.  
Figure 12: Basic Interrupt Structure  
INTR  
T1PND  
T1  
T0PND  
T0  
Interrupt  
WKPND  
MIW  
Interrupt  
Pending  
Flags  
T0INT  
EN  
WKINT  
EN  
G
T1EN  
Global Interrupt  
Enable  
Interrupt Enable Bits  
12  
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ACE8001 Product Family Rev. B.2  
stacked and the G bit is cleared. This means, if the G bit was  
enabled prior to the software interrupt the RETI instruction must  
be used to return from interrupt in order to restore the G bit to its  
previous state. However, if the G bit was not enabled prior to the  
software interrupt the RET instruction must be used.  
Negative (N)  
The negative flag is set if the MSB of the result from an arith-  
metic, logic, or data manipulation operation is set to one. Other-  
wise, the flag is cleared. A result is said to be negative if its MSB  
is a one.  
In case of multiple interrupts occurring at the same time, the  
ACEx microcontroller core has prioritized the interrupts. The  
interrupt priority sequence in shown in Table 6.  
Interrupt Mask (G)  
The interrupt request mask (G) is a global mask that disables all  
maskable interrupt sources. If the G Bit is cleared, interrupts  
can become pending, but the operation of the core continues  
uninterrupted. However, if the G Bit is set an interrupt is recog-  
nized. After any reset, the G bit is cleared by default and can  
only be set by a software instruction. When an interrupt is rec-  
ognized, the G bit is cleared after the PC is stacked and the  
interrupt vector is fetched. Once the interrupt is serviced, a  
return from interrupt instruction is normally executed to restore  
the PC to the value that was present before the interrupt  
occurred. The G bit is the reset to one after a return from inter-  
rupt is executed. Although the G bit can be set within an inter-  
rupt service routine, “nesting” interrupts in this way should only  
be done when there is a clear understanding of latency and of  
the arbitration mechanism.  
4.3 Addressing Modes  
The ACEx microcontroller has six addressing modes indexed,  
direct, immediate, absolute jump, and relative jump.  
Indexed  
The instruction allows an 8-bit unsigned offset value to be  
added to the 10-LSBs of the X-pointer yielding a new effective  
address. This mode can be used to address any memory space  
(program or data).  
Direct  
The instruction contains an 8-bit address field that directly  
points to the data memory space as an operand.  
4.2 Interrupt handling  
Immediate  
When an interrupt is recognized, the current instruction com-  
pletes its execution. The return address (the current value in the  
program counter) is pushed onto the stack and execution con-  
tinues at the address specified by the unique interrupt vector  
(see Table 9). This process takes five instruction cycles. At the  
end of the interrupt service routine, a return from interrupt  
(RETI) instruction is executed. The RETI instruction causes the  
saved address to be pulled off the stack in reverse order. The G  
bit is set and instruction execution resumes at the return  
address.  
The instruction contains an 8-bit immediate field as an operand.  
Inherent  
This instruction has no operands associated with it.  
Absolute  
The instruction contains a 10-bit address that directly points to a  
location in the program memory space. There are two operands  
associated with this addressing mode. Each operand contains a  
byte of an address. This mode is used only for the long jump  
(JMP) and JSR instructions.  
The ACEx microcontroller is capable of supporting four inter-  
rupts. Three are maskable through the G bit of the SR and the  
fourth (software interrupt) is not inhibited by the G bit (see Fig-  
ure 12). The software interrupt is generated by the execution of  
the INTR instruction. Once the INTR instruction is executed, the  
ACEx core will interrupt whether the G bit is set or not. The  
INTR interrupt is executed in the same manner as the other  
maskable interrupts where the program counter register is  
Relative  
This mode is used for the short jump (JP) instructions where the  
operand is a value relative to the current PC address. With this  
instruction, software is limited to the number of bytes it can  
jump, -31 or +32.  
Table 6: Interrupt Priority Sequence  
Priority (4 highest, 1 lowest)  
Interrupt  
MIW (EDGEI)  
4
3
2
1
Timer0 (TMRI0)  
Timer1 (TMRI1)  
Software (INTR)  
13  
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ACE8001 Product Family Rev. B.2  
Table 7: Instruction Addressing Modes  
Instruction  
Immediate  
Direct  
Indexed  
Inherent  
Relative Absolute  
ADC  
AND  
SUBC  
XOR  
A, #  
A, #  
A, #  
A, #  
A, M  
A, M  
A, M  
A, M  
CLR  
INC  
DEC  
M
M
M
A
A
A
X
X
IFEQ  
IFGT  
IFNE  
A, #  
A, #  
A, #  
M,#  
A, M  
A, M  
A, M  
SC  
RC  
IFC  
IFNC  
INVC  
LDC  
STC  
no-op  
no-op  
no-op  
no-op  
no-op  
#, M  
#, M  
RLC  
RRC  
A
A
LD  
ST  
LD  
A, #  
M, #  
X, #  
A, M  
A, M  
M, M  
A, [00,X]  
A, [00,X]  
NOP  
no-op  
IFBIT  
SBIT  
RBIT  
#, M  
#, M  
#, M  
JP  
Rel  
JSR  
JMP  
RET  
RETI  
INTR  
M
M
no-op  
no-op  
no-op  
14  
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ACE8001 Product Family Rev. B.2  
Table 8: Instruction Cycles and Bytes  
Flags  
Mnemonic Operand Bytes Cycles affected  
Flags  
Mnemonic Operand Bytes Cycles affected  
ADC  
ADC  
AND  
AND  
CLR  
CLR  
DEC  
DEC  
DEC  
IFBIT  
IFC  
A, #  
A, M  
A, #  
A, M  
A
2
2
2
2
1
2
1
2
1
2
1
2
2
3
2
2
2
2
1
1
2
1
1
1
3
2
2
2
2
1
1
1
2
1
2
1
2
2
3
2
2
2
2
1
1
2
1
5
1
4
C,H,Z,N  
C,H,Z,N  
Z,N  
JP  
1
3
2
2
2
3
3
3
2
1
2
1
1
1
1
1
2
1
2
2
2
2
2
2
2
1
5
2
3
2
3
3
3
2
1
2
1
5
5
1
1
2
1
3
2
2
2
2
2
2
None  
None  
None  
None  
None  
None  
None  
None  
C
JSR  
LD  
M
A, #  
Z,N  
LD  
A, [00,X]  
A, M  
M, #  
M, M  
X, #  
Z,N,C,H  
Z,N,C,H  
Z,N  
LD  
M
LD  
A
LD  
M
Z,N  
LD  
X
Z
LDC  
NOP  
RBIT  
RC  
#, M  
#, M  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
Z,N  
None  
Z,N  
#, M  
IFEQ  
IFEQ  
IFEQ  
IFGT  
IFGT  
IFNE  
IFNE  
IFNC  
INC  
A, #  
A, M  
M, #  
A, #  
A, M  
A, #  
A, M  
C,H  
RET  
RETI  
RLC  
RRC  
SBIT  
SC  
None  
None  
C,Z,N  
C,Z,N  
Z,N  
A
A
#, M  
C,H  
ST  
A, [00,X]  
A, M  
#, M  
None  
None  
Z,N  
A
M
X
ST  
INC  
Z,N  
STC  
SUBC  
SUBC  
XOR  
XOR  
INC  
Z
A, #  
C,H,Z,N  
C,H,Z,N  
Z,N  
INTR  
INVC  
JMP  
None  
C
A, M  
A, #  
M
None  
A, M  
Z,N  
15  
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ACE8001 Product Family Rev. B.2  
4.4 Memory Map  
All I/O ports, peripheral registers and core registers (except the accumulator and the program counter) are mapped into memory  
space.  
Table 9: Memory Map  
Address  
Memory Space  
Block  
SRAM  
Contents  
0x00 - 0x3F  
Data  
Data  
Data  
Data RAM  
0x40 - 0x7F  
0xAA  
EEPROM  
Timer1  
Data EEPROM  
T1RA register  
0xAB, 0xAD  
0xAC  
Reserved  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Timer1  
Timer1  
MIW  
TMR1 register  
0xAE  
T1CNTRL register  
WKEDG register  
WKPND register  
WKEN register  
0xAF  
0xB0  
MIW  
0xB1  
MIW  
0xB2  
I/O  
PORTGD register  
PORTGC register  
PORTGP register  
WDSVR register  
T0CNTRL register  
HALT mode register  
Reserved  
0xB3  
I/O  
0xB4  
I/O  
0xB5  
Timer0  
Timer0  
Clock  
0xB6  
0xB7  
0xB8 - 0xBA  
0xBB  
Data  
Data  
Init. Reg.  
Init. Reg.  
LBD  
Initialization register 1  
Initialization register 2  
LBD register  
0xBC  
0xBD  
Data  
0xBE  
Data  
Core  
XHI register  
0xBF  
Data  
Core  
XLO register  
0xC0  
Data  
Clock  
Core  
Power mode clear (PMC) register  
SP register  
0xCE  
Data  
0xCF  
Data  
Core  
Status register (SR)  
Code EEPROM  
Timer0 Interrupt vector  
Timer1 Interrupt vector  
MIW Interrupt vector  
Soft Interrupt vector  
Reserved  
0xC00 - 0xFF5  
0xFF6 - 0xFF7  
0xFF8 - 0xFF9  
0xFFA - 0xFFB  
0xFFC - 0xFFD  
0xFFE - 0xFFF  
Program  
Program  
Program  
Program  
Program  
EEPROM  
Core  
Core  
Core  
Core  
16  
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ACE8001 Product Family Rev. B.2  
4.5 Memory  
4.6 Initialization Registers  
The ACEx microcontroller device has 64 bytes of SRAM and 64  
bytes of EEPROM available for data storage. The device also  
has 1K bytes of EEPROM for program storage. Software can  
read and write to SRAM and data EEPROM but can only read  
from the code EEPROM. While in normal mode, the code  
EEPROM is protected from any writes. The code EEPROM can  
only be rewritten when the device is in program mode and if the  
write disable (WDIS) bit of the initialization register is not set to  
1.  
The ACEx microcontroller has two 8-bit wide initialization regis-  
ters. These registers are read from the memory space on  
power-up to initialize certain on-chip peripherals. Figure 13 pro-  
vides a detailed description of Initialization Register 1. The Ini-  
tialization Register 2 is used to trim the internal oscillator to its  
appropriate frequency. This register is pre-programmed in the  
factory to yield an internal instruction clock of 1MHz.  
Both Initialization Registers 1 and 2 can be read from and writ-  
ten to during programming mode. However, re-trimming the  
internal oscillator (writing to the Initialization Register 2) once it  
has left the factory is discouraged.  
While in normal mode, the user can write to the data EEPROM  
array by 1) polling the ready (R) flag of the SR, then 2) execut-  
ing the appropriate instruction. If the R flag is 1, the data  
EEPROM block is ready to perform the next write. If the R flag is  
0, the data EEPROM is busy. The data EEPROM array will reset  
the R flag after the completion of a write cycle. Attempts to read,  
write, or enter HALT/IDLE mode while the data EEPROM is  
busy (R = 0) can affect the current data being written.  
Figure 13: Initialization Register 1  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
7
8,9  
8,9  
8,9  
CMODE[0:1]  
WDEN  
BOREN  
BLSEL  
UBD  
WDIS  
RDIS  
8,9  
8,9  
(0) RDIS  
(1) WDIS  
If set, disables attempts to read the contents from the EEPROMs while in programming mode  
If set, disables attempts to write new contents to the EEPROMs while in programming mode  
8,9  
(2) UBD  
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)  
7
(3) BLSEL  
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for the ACE8001  
If not set, the BOR voltage reference level is set to its lower range  
(4) BOREN  
(5) WDEN  
If set, allows a BOR to occur if V falls below the voltage reference level  
CC  
If set, enables the on-chip processor watchdog circuit  
Clock mode select bit 1 (See table 13)  
(6) CMODE[1]  
(7) CMODE[0]  
Clock mode select bit 0 (See table 13)  
7
The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain bits set value.  
If both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.  
8
9
If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.  
17  
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ACE8001 Product Family Rev. B.2  
timer underflow (transitions from 0x00 to 0xFF or reload) can  
either generate an interrupt and/or toggle the T1 output pin.  
5.0 Timer 1  
Timer 1 is a versatile 8-bit timer. Its main function is to operate  
as a Pulse Width Modulation (PWM) generator that generates  
pulses of a specified width and duty cycles.  
Timer 1’s interrupt (TMRI1) can be enabled by the interrupt  
enable (T1EN) bit in the T1CNTRL register. When the timer  
interrupt is enabled, the source of the interrupt is a timer under-  
flow. By default, the timer register is reset to 0xFF and the auto-  
reload register is reset to 0x00.  
Timer 1 contains an 8-bit timer register (TMR1), an 8-bit auto-  
reload register (T1RA), and an 8-bit control register  
(T1CNTRL). All registers are memory-mapped for simple  
access through the core. For the PWM signal generation the  
timer contains an output (T1) that is multiplexed with the I/O pin  
G2.  
5.1 Timer control bits  
Reading and writing to the T1CNTRL register controls the  
timer’s operation. By writing to the control bits, the user can  
enable or disable the timer interrupts, set the mode of operation,  
start or stop the timer, and select the clock. The T1CNTRL reg-  
ister bits are described in Table 10.  
The timer can be started or stopped through the T1CNTRL reg-  
ister bit T1C0. When running, the timer counts down (decre-  
ments) every clock cycle. The timer’s clock has a pre-scalar and  
is selectable through two T1CNTRL register bits T1PSC[1:0].  
Depending on the selected operating mode, occurrences of  
Table 10:TIMER1 Control Register Bits  
T1CNTRL Register  
Name  
-----------  
-----------  
T1C1  
Function  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Reserved  
Reserved  
T1 toggle enable bit: 1 = T1 toggle enabled, 0 = T1 toggle disabled  
TMR1 run: 1 = Start timer, 0 = Stop timer  
T1C0  
T1PND  
Timer1 interrupt pending flag: 1 = Timer1 interrupt  
pending, 0 = Timer1 interrupt not pending  
Bit 2  
T1EN  
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,  
0 = Timer1 interrupt disabled  
Bit 1,0  
T1PSC  
Pre-scalar selection bits: Selects the 1MHz clock divider to be by 1 (00b),  
2 (01b), 4 (10b), or 8 (11b)  
18  
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ACE8001 Product Family Rev. B.2  
1. Configure T1 as an output by setting bit 2 of PORTGC.  
- SBIT 2, PORTGC ; Configure G2 as an output  
5.2 Pulse Width Modulation (PWM) Mode  
In the PWM mode, the timer counts down at the instruction  
clock rate. When an underflow occurs, the timer register is  
reloaded from T1RA and the count down proceeds from the  
loaded value. At every underflow, a pending flag (T1PND)  
located in the T1CNTRL register is set. Software must then  
clear the T1PND flag and load the T1RA register with an alter-  
nate PWM value. In addition, the timer can be configured to tog-  
gle the T1 output bit upon underflow. Configuring the timer to  
toggle T1 results in the generation of a signal outputted from  
port G2 with the width and duty cycle controlled by the values  
stored in the T1RA. A block diagram of the timer’s PWM mode  
of operation is shown in Figure 14.  
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of  
PORTGD.  
- SBIT 2, PORTGD  
; Set G2 high  
3. Load the initial PWM high (low) time into the timer register.  
- LD TMR1, #6FH  
; High (Low) for .444ms  
(1MHz/4 clock)  
4. Load the PWM low (high) time into the T1RA register.  
- LD T1RA, #2FH  
; Low (High) for .188ms  
(1MHz/4 clock)  
5. Write the appropriate control value to the T1CNTRL register  
to select PWM mode with T1 toggle, to select the divide by 4  
pre-scalar, and to clear the enable and pending flags. (See  
Table 12)  
The timer has one interrupt (TMRI1) that is maskable through  
the T1EN bit of the T1CNTRL register. However, the core is only  
interrupted if the T1EN bit and the G (Global Interrupt enable)  
bit of the SR is set. If interrupts are enabled, the timer will gen-  
erate an interrupt each time T1PND flags is set (whenever the  
timer underflows provided that the pending flag was cleared.)  
The interrupt service routine is responsible for proper handling  
of the T1PND flag and the T1EN bit.  
- LD T1CNTRL, #22H  
; Setting the T1C0 bit starts  
the timer  
6. Set the T1CO bit to start the timer.  
- SBIT T1CP, T1CNTRL  
; T1CO equals 4  
7. After every underflow, load T1RA with alternate values. If the  
user wishes to generate an interrupt on timer output transi-  
tions, reset the pending flags and then enable the interrupt  
using T1EN. The G bit must also be set. The interrupt ser-  
vice routine must reset the pending flag and perform what-  
ever processing is desired.  
The interrupt will be synchronous with every rising and falling  
edge of the T1 output signal. Generating interrupts only on ris-  
ing or falling edges of T1 is achievable through appropriate han-  
dling of the T1EN bit or T1PND flag through software.  
The following steps show how to properly configure Timer 1 to  
operate in the PWM mode. For this example, the T1 output sig-  
nal is toggled with every timer underflow and the “high” and  
“low” times for the T1 output can be set to different values. The  
T1 output signal can start out either high or low depending on  
the configuration of I/O G2; the instructions below are for start-  
ing with the T1 output high. Follow the instructions in parenthe-  
ses to start the T1 output low.  
- RBIT T1PND, T1CNTRL ; T1PND equals 3  
- LD T1RA, #6FH  
; Low for .444ms  
(1MHz/4 clock)  
Figure 14: Pulse Width Modulation Mode  
Underflow  
Interrupt  
8-bit Auto-Reload  
Register (T1RA)  
Data  
Latch  
T1  
Data  
Bus  
Instruction  
Clock  
÷ 8  
÷ 4  
÷ 2  
3
2
1
0
8-bit Timer  
(TMR1)  
Sel  
T1PSC[1:0]  
19  
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ACE8001 Product Family Rev. B.2  
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt  
block. See Section 8.0 for details.  
6.0 Timer 0  
Timer 0 is a 12-bit free running idle timer. Upon power-up or any  
reset, the timer is reset to 0x000 and then counts up continu-  
ously based on the instruction clock of 1MHz (1 µs). Software  
cannot read from or write to this timer. However, software can  
monitor the timer’s pending (T0PND) bit that is set every 8192  
cycles (initially 4096 cycles after a reset or after the watchdog  
has been- serviced). The T0PND flag is set every other time the  
timer overflows (transitions from 0xFFF to 0x000). After an over-  
flow, the timer will reset and restart its counting sequence.  
7.0 Watchdog  
The Watchdog timer is used to reset the device and safely  
recover in the rare event of a processor “runaway condition.”  
The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer.  
The Watchdog timer must be serviced before every 61,440  
cycles but no sooner than 4096 cycles since the last Watchdog  
reset. The Watchdog is serviced through software by writing the  
value 0x1B to the Watchdog Service (WDSVR) register (see  
Figure 16). The part resets automatically if the Watchdog is ser-  
viced too frequent, or not frequent enough.  
Software can either poll the T0PND bit or vector to an interrupt  
subroutine. In order to interrupt on a T0PND, software must be  
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the  
Timer 0 control (T0CNTRL) register and also make sure the G  
bit is set in SR. Once the timer interrupt is serviced, software  
should reset the T0PND bit before exiting the routine. Timer 0  
supports the following functions:  
The Watchdog timer must be enabled through the Watchdog  
enable bit (WDEN) in the initialization register. The WDEN bit  
can only be set while the device is in programming mode. Once  
set, the Watchdog will always be powered-up enabled. Software  
cannot disable the Watchdog. The Watchdog timer can only be  
disabled in programming mode by resetting the WDEN bit as  
long as the memory write protect (WDIS) feature is not enabled.  
1. Exiting from IDLE mode (See Section 16.0 for details.)  
2. Start up delay from HALT mode  
WARNING  
3. Watchdog pre-scalar (See Section 7.0 for details.)  
Ensure that the Watchdog timer has been serviced before  
entering IDLE mode because it remains operational during this  
time.  
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests  
from the Timer 0 are ignored. If set to 1, interrupt requests are  
accepted. Upon reset, the T0INTEN bit is reset to 0.  
The T0PND bit is a read/write bit. If set to 1, it indicates that a  
Timer 0 interrupt is pending. This bit is set by a Timer 0 overflow  
and is reset by software or system reset.  
Figure 15:Timer 0 Control Register Definition (T0CNTRL)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
WKINTEN  
x
x
x
x
x
T0PND  
T0EN  
Figure 16:Watchdog Server Register (WDSVR)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
1
1
0
1
1
20  
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ACE8001 Product Family Rev. B.2  
6. Set the WKEN bits associated with the pins to be used, thus  
enabling those pins for the Wakeup/Interrupt function.  
8.0 Multi-Input Wakeup/Interrupt Block  
The Multi-Input Wakeup (MIW)/Interrupt contains three mem-  
ory-mapped registers associated with this circuit: WKEDG  
(Wakeup Edge), WKEN (Wakeup Enable), and WKPND  
(Wakeup Pending). Each register has three bits with each bit  
corresponding to an input pins as shown in Figure 17. All three  
registers are initialized to zero upon reset.  
-LD WKEN, #38H  
;Enabling G3, G4, G5  
Once the Multi-Input Wakeup/Interrupt function has been config-  
ured, a transition sensed on any of the enabled pins will set the  
corresponding bit in the WKPND register. The WKPND bits can  
bring the device out of the HALT/IDLE mode and can also trigger  
an interrupt if the interrupt is enabled. The interrupt service routine  
can read the WKPND register to determine which pin sensed the  
interrupt.  
The WKEDG register establishes the edge sensitivity for each  
of the wake-up input pin: either (0) rising edge or (1) falling  
edge.  
The interrupt service routine or other software should clear the  
pending bit. The device will not enter HALT/IDLE mode as long as  
a WKPND pending bit is pending and enabled. The user has the  
responsibility of clearing the pending flags before attempting to  
enter the HALT/IDLE mode.  
The WKEN register enables (1) or disables (0) each of the port  
pins for the Wakeup/Interrupt function. The wakeup I/Os used  
for the Wakeup/Interrupt function must also be configured as an  
input pin in its associated port configuration register. However,  
an interrupt (EDGE1) of the core will not occur unless interrupts  
are enabled for the block via bit 7 of the T0CNTRL register (see  
Figure 15) and the G (global interrupt enable) bit of the SR is  
set.  
Upon reset, the WKEDG register is configured to select positive-  
going edge sensitivity for all wakeup inputs. If the user wishes to  
change the edge sensitivity of a port pin, use the following proce-  
dure to avoid false triggering of a Wakeup/Interrupt condition.  
The WKPND register contains the pending flags corresponding  
to each of the port pins (1 for wakeup/interrupt pending, 0 for  
wakeup/interrupt not pending).  
1. Clear the WKEN bit associated with the pin to disable that pin.  
2. Write the WKEDG register to select the new type of edge sensi-  
tivity for the pin.  
To use the Multi-Input Wakeup/Interrupt circuit, perform the  
steps listed below. Performing the steps in the order shown will  
prevent false triggering of a Wakeup/Interrupt condition. This  
same procedure should be used following any type of reset  
because the wakeup inputs are left floating after resets resulting  
in unknown data on the port inputs.  
3. Clear the WKPND bit associated with the pin.  
4. Set the WKEN bit associated with the pin to re-enable it.  
PORTG provides the user with three fully selectable, edge sensi-  
tive interrupts that are all vectored into the same service subrou-  
tine. The interrupt from PORTG shares logic with the wakeup  
circuitry. The WKEN register allows interrupts from PORTG to be  
individually enabled or disabled.The WKEDG register specifies the  
trigger condition to be either a positive or a negative edge. The  
WKPND register latches in the pending trigger conditions.  
1. Clear the WKEN register.  
-CLR WKEN  
2. If necessary, write to the port configuration register to select  
the desired port pins to be configured as inputs.  
-RBIT 4, PORTGC  
;G3, G4, and/or G5  
Since PORTG is also used for exiting the device from the HALT/  
IDLE mode, the user can elect to exit the HALT/IDLE mode either  
with or without the interrupt enabled. If the user elects to disable  
the interrupt, then the device restarts execution from the point at  
which it was stopped (first instruction cycle of the instruction follow-  
ing HALT/IDLE mode entrance instruction). In the other case, the  
device finishes the instruction that was being executed when the  
part was stopped and then branches to the interrupt service rou-  
tine.The device then reverts to normal operation.  
3. If necessary, write to the port data register to select the  
desired port pins input state.  
-SBIT 4, PORTGD  
;Pull-up  
4. Write the WKEDG register to select the desired type of edge  
sensitivity for each of the pins used.  
-LD WKEDG, #38H  
;Falling edges  
5. Clear the WKPND register to cancel any pending bits.  
-CLR WKPND  
Figure 17: MIW Register Bit Assignments  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
x
x
G5  
G4  
G3  
x
x
x
Figure 18: Multi-input Wakeup (MIW) Block Diagram  
Data Bus  
5
4
3
WKEN[5:3]  
WKOUT  
EDGEI  
3
4
G3  
G4  
G5  
5
WKEDG[3:5]  
WKPND[3:5]  
WKINTEN10  
10  
WKINTEN: Bit 7 of T0CNTR  
21  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
ter (PORTGC), a port data register (PORTGD), and a port input  
register (PORTGP). PORTGC is used to configure the pins as  
inputs or outputs. A pin may be configured as an input by writing  
a 0 or as an output by writing a 1 to its corresponding PORTGC  
bit. If a pin is configured as an output, its PORTGD bit repre-  
sents the state of the pin (1 = logic high, 0 = logic low). If the pin  
is configured as an input, its PORTGD bit selects whether the  
pin is a weak pull-up or a high-impedence input. Table 11 pro-  
vides details of the port configuration options. The port configu-  
ration and data registers are both read/writable. Reading  
PORTGP returns the value of the port pins regardless of how  
the pins are configured. Since this device supports multi-input  
wakeup/interrupt, the PORTG inputs have Schmitt triggers.  
9.0 I/O Port  
The six I/O pins are bi-directional with the exception of G3  
which is always an input with weak pull-up (see Figure 19). The  
bi-directional I/O pins can be individually configured by software  
to operate as high-impedance inputs, as inputs with weak pull-  
up, or as push-pull outputs. The operating state is determined  
by the contents of the corresponding bits in the data and config-  
uration registers. Each bi-directional I/O pin can be used for  
general purpose I/O, or in some cases, for a specific alternate  
function determined by the on-chip hardware.  
9.1 I/O registers  
The I/O pins (G0-G5) have three memory-mapped port regis-  
ters associated with the I/O circuitry: a port configuration regis-  
Figure 19: PORTGD Logic Diagram  
Weak Pull-up Control  
PORTGC  
PIN GX  
PORTGD  
PORTGP  
Figure 20: I/O Register bit assignments  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12  
11  
x
x
G5  
G4  
G3  
G2  
G1  
G0  
Table 11: I/O configuration options  
Configuration Bit  
Data Bit  
Port Pin Configuration  
0
0
1
1
0
1
0
1
High-impedence input (TRI-STATE input)  
Input with pull-up (weak one input)  
Push-pull zero output  
Push-pull one output  
11  
12  
G3 is only an input  
G5 is not available on SOIC-8 package with the reset pin option (ACE8000)  
22  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
13,14  
programmer has sent the second rising edge during the LOAD  
= 0V phase (if the timing specifications in Figure 21 are  
obeyed).  
10.0 In-circuit Programming Specification  
The ACEx microcontroller supports in-circuit programming of  
the internal data EEPROM, code EEPROM, and the initializa-  
tion registers.  
The device will set the R bit of the Status register when the write  
operation has completed. The external programmer must wait  
for the SHIFT_OUT pin to go high before bringing the LOAD sig-  
nal to 5V to initiate a normal command cycle.  
An externally controlled four wire interface consisting of a LOAD  
control pin (G3), a serial data SHIFT-IN input pin (G4), a serial  
data SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is  
used to access the on-chip memory locations. Communication  
between the ACEx microcontroller and the external programmer  
10.2 Read Sequence  
When reading the device after a write, the external programmer  
must set the LOAD signal to 5V before it sends the new com-  
mand word. Next, the 32-bit serial command word (for during a  
READ) should be shifted into the device using the SHIFT_IN  
and the CLOCK signals while the data from the previous com-  
mand is serially shifted out on the SHIFT_OUT pin. After the  
Read command has been shifted into the device, the external  
programmer must, once again, set the LOAD signal to 0V and  
apply two clock pulses as shown in Figure 21 to complete  
READ cycle. Data from the selected memory location, will be  
latched into the lower 8 bits of the command word shortly after  
the second rising edge of the CLOCK signal.  
is made through  
described in Table 12.  
a 32-bit command and response word  
The serial data timing for the four-wire interface is shown in Fig-  
ure 22 and the programming protocol is shown in Figure 21.  
10.1 Write Sequence  
The external programmer brings the ACEx microcontroller into  
programming mode by applying a super voltage level to the  
LOAD pin. The external programmer then needs to set the  
LOAD pin to 5V before shifting in the 32-bit serial command  
word using the SHIFT_IN and CLOCK signals. By definition, bit  
31 of the command word is shifted in first. At the same time, the  
ACEx microcontroller shifts out the 32-bit serial response to the  
last command on the SHIFT_OUT pin. It is recommended that  
Writing a series of bytes to the device is achieved by sending a  
series of Write command words while observing the devices  
handshaking requirements.  
the external programmer samples this signal t  
(1µs) after  
ACCESS  
Reading a series of bytes from the device is achieved by send-  
the rising edge of the CLOCK signal. The serial response word,  
sent immediately after entering programming mode, contains  
indeterminate data.  
ing  
a series of Read command words with the desired  
addresses in sequence and reading the following response  
words to verify the correct address and data contents.  
After 32 bits have been shifted into the device, the external pro-  
grammer must set the LOAD signal to 0V, and then apply two  
clock pulses as shown in Figure 21 to complete program cycle.  
The SHIFT_OUT pin acts as the handshaking signal between  
the device and programming hardware once the LOAD signal is  
brought low. The device sets SHIFT_OUT low by the time the  
The addresses of the data EEPROM and code EEPROM loca-  
tions are the same as those used in normal operation.  
Powering down the device will cause the part to exit program-  
ming mode.  
Table 12: 32-Bit Command and Response Word  
Bit number  
bits 31 – 30  
bit 29  
Input command word  
Output response word  
Must be set to 0  
X
Set to 1 to read/write data EEPROM, or the initializa-  
tion registers, otherwise 0  
X
bit 28  
Set to 1 to read/write code EEPROM, otherwise 0  
Must be set to 0  
X
bits 27 – 25  
bit 24  
X
Set to 1 to read, 0 to write  
X
bits 23 – 18  
bits 17 – 8  
bits 7 – 0  
Must be set to 0  
X
Address of the byte to be read or written  
Data to be programmed or zero if data is to be read  
Same as Input command word  
Programmed data or data read at specified address  
13  
Application Note reference: “How to In-Circuit Program the ACEx Family of Microcontrollers.”  
14  
During in-circuit programming, G5 must be either not connected or driven high.  
23  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
13  
Figure 21: Programming Protocol  
A
A
tSV1 tSV2  
tload1 tload2  
tready  
tload3 tload4  
enter prog.  
mode  
LOAD (G3)  
32 clock pulses  
CLOCK (G1)  
bit 31  
bit 30  
bit 0  
bit 31  
SHIFT_IN (G4)  
BUSY low by  
2nd clock pulse  
READY  
SHIFT_OUT (G2)  
(in write mode)  
BUSY  
SHIFT_OUT (G2)  
(in read mode)  
A: start of programming cycle  
Figure 22: Serial Data Timing  
tHI  
tLO  
CLOCK (G1)  
tDIS  
tDIH  
Valid  
SHIFT_IN (G4)  
tDOS  
tDOH  
Valid  
SHIFT_OUT (G2)  
tACCESS  
24  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
BOR will always be powered-up enabled. Software cannot dis-  
able the BOR. The BOR can only be disabled in programming  
mode by resetting the BOREN bit as long as the global write  
protect (WDIS) feature is not enabled.  
11.0 Brown-out/Low Battery Detect Circuit  
The Brown-out Reset (BOR) and Low Battery Detect (LBD) cir-  
cuits on the ACEx microcontroller have been designed to offer  
two types of voltage reference comparators. The sections below  
will describe the functionality of both circuits.  
11.2 Low Battery Detect  
The Low Battery Detect (LBD) circuit allows software to monitor  
11.1 Brown Out Reset  
the V  
level at the lower voltage ranges. LBD has eight soft-  
CC  
The Brown-out Reset (BOR) function is used to hold the device  
ware programmable voltage reference threshold levels ranging  
from 2.0V (Bat_tri[2:0] set to zero) to 3.6V (Bat_trim[2:0] set to  
in reset when V drops below a fixed threshold. While in reset,  
CC  
the device is held in its initial condition until V rises above the  
threshold value. Shortly after V  
value, an internal reset sequence is started. After the reset  
sequence, the core fetches the first instruction and starts nor-  
mal operation.  
CC  
one) that can be changed on the fly. Once V  
falls below the  
CC  
rises above the threshold  
CC  
selected threshold, the LBD flag in the LBD control register is  
set. The LBD flag will hold its value until V  
rises above the  
CC  
threshold. (See Figure 23)  
The LBD bit is read only. If LBD is 0, it indicates that the V  
CC  
On the devices, the BOR should be used in situations when V  
CC  
level is higher than the selected threshold. If LBD is 1, it indi-  
cates that the V level is below the selected threshold. The  
rises and falls slowly and in situations when V does not fall to  
CC  
CC  
zero before rising back to operating range. The BOR can be  
thought of as a supplement function to the Power-on Reset  
threshold level can be adjusted up to eight levels using the three  
trim bits (Bat_trim[2:0]) of the LBD control register.The LBD flag  
does not cause any hardware actions or an interruption of the  
processor. It is for software monitoring only.  
when V does not fall below ~1.5V. The Power-on Reset circuit  
CC  
works best when V  
starts from 0V and rises sharply. So in  
CC  
applications where V is not constant, the BOR will give added  
CC  
The LBD function is disabled during HALT/IDLE mode. After  
exiting HALT/IDLE, software must wait at lease 10µs before  
reading the LBD bit to ensure that the internal circuit has stabi-  
lized.  
device stability.  
The BOR circuit must be enabled through the BOR enable bit  
(BOREN) in the initialization register. The BOREN bit can only  
be set while the device is in programming mode. Once set, the  
Figure 23: LBD Control Register Definition  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Bat_trim[2:0]  
0
X
X
X
LBD  
Figure 24: BOR/LBD Block Diagram  
Vcc  
0
1.8V  
2.2V  
_
+
1
BOR  
to RESET logic  
S
BLSEL16  
_
+
Adjust Reference Voltage  
LBD  
LBD  
7
6
5
4
3
2
1
0
Control  
Register  
16  
See Figure 13 for information on BLSEL.  
25  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
12.0 RESET block  
14.0 CLOCK  
When a RESET sequence is initiated, all I/O registers will be  
reset setting all I/Os to high-impedence inputs. The system  
clock is restarted after the required clock start-up delay. A reset  
is generated by any one of the following three conditions:  
The ACEx microcontroller has an on-board oscillator trimmed to  
a frequency of 2MHz who is divided down by two yielding a  
1MHz frequency.(See AC Electrical Characteristics.) Upon  
power-up, the on-chip oscillator runs continuously unless enter-  
ing HALT mode or using an external clock source. (See Figure  
26.)  
• Power-on Reset (as described in Section 13.0)  
• Brown-out Reset (as described in Section 11.1)  
• Watchdog Reset (as described in Section 7.0)  
If required, an external oscillator circuit may be used depending  
on the states of the CMODE bits of the initialization register.  
(See Table 13) When the device is driven using an external  
clock, the clock input to the device (G1/CKI) can range between  
DC to 4MHz. For external crystal configuration, the output clock  
(CKO) is on the G0 pin. If an external crystal or RC is used, to  
yield the corresponding instruction clock the input frequency is  
internally divided down by four. If the device is configured for an  
external square clock, it will not be divided.  
15  
• External Reset (as described in Section 13.0)  
13.0 Power-On-Reset  
The Power-On Reset (POR) circuit is guaranteed to work if the  
rate of rise of V is no slower than 10ms/1volt. The POR circuit  
CC  
was designed to respond to fast low to high transitions between  
0V and V . The circuit will not work if V does not drop to 0V  
CC  
CC  
before the next power-up sequence. In applications where 1)  
the V rise is slower than 10ms/1 volt or 2) V does not drop  
CC  
CC  
to 0v before the next power-up sequence the external reset  
option should be used. The external reset option provides a way  
to properly reset the ACEx microcontroller if POR cannot be  
used in the application. The external reset pin contains an inter-  
nal pull-up resistor.  
Table 13: CMODE[0:1] Bit Definition  
CMODE[0]  
CMODE[1]  
Clock Type  
Internal 1 MHz clock  
External square clock  
External RC clock  
0
1
1
0
0
1
Figure 25: BOR and POR Circuit Relationship Diagram (see AC Electrical Characteristics)  
V
(Pin 8)  
CC  
BOR  
output  
V
CC  
V
1.75  
CC  
0
V
CC  
0
Global Reset  
to Logic  
Time  
BOR Output  
Reset  
circuit  
output  
A
POR  
output  
External  
Reset  
B
The Reset circuit will trigger  
when inputs A or B transition  
from High to Low. At that time  
the Global Reset signal will go  
high which will reset all controller  
logic. The Global Reset will go  
high and stay high for around 1µs.  
Pin  
V
CC  
(14-Pin Only)  
5.0V  
1.8V  
0
(Pin 7)  
V
CC  
POR Output  
Pulse  
POR  
output  
0
15  
Available as option on SOIC-8 package only, it replaces the port G5  
26  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
Figure 26: RC Oscillator Diagrams  
CKI  
(G1)  
CKO  
(G0)  
R
VCC  
C
15.0 HALT Mode  
16.0 IDLE Mode  
The HALT mode is a power saving feature that almost com-  
pletely shuts down the device for current conservation. The  
device is placed into HALT mode by setting the HALT enable bit  
(EHALT) of the HALT register through software using only the  
“LD M, #” instruction. EHALT is a write only bit and is automati-  
cally cleared upon exiting HALT. When entering HALT, the inter-  
nal oscillator and all the on-chip systems including the LBD and  
the BOR circuits are shut down.  
In addition to the HALT mode power saving feature, the device  
also supports an IDLE mode operation. The device is placed  
into IDLE mode by setting the IDLE enable bit (EIDLE) of the  
HALT register through software using only the “LD M, #” instruc-  
tion. EIDLE is a write only bit and is automatically cleared upon  
exiting IDLE. The IDLE mode operation is similar to HALT  
except the internal oscillator, the Watchdog, and the Timer 0  
remain active while the other on-chip systems including the LBD  
and the BOR circuits are shut down.  
The device can exit HALT mode only by the MIW circuit. There-  
fore, prior to entering HALT mode, software must configure the  
MIW circuit accordingly. (See Section 8.0) After a wakeup from  
HALT, a 64 clock cycle start-up delay is initiated to allow the  
internal oscillator to stabilize before normal execution resumes.  
Immediately after exiting HALT, software must clear the Power  
Mode Clear (PMC) register by only using the “LD M, #” instruc-  
tion. (See Figure 28)  
The device can exit IDLE by a Timer 0 overflow every 8192  
cycles or/and by the MIW circuit. If exiting IDLE mode with the  
MIW, prior to entering, software must configure the MIW circuit  
accordingly. (See Section 8.0) Once a wake from IDLE mode is  
triggered, the core will begin normal operation by the next clock  
cycle. Immediately after exiting IDLE mode, software must clear  
the Power Mode Clear (PMC) register by using only the “LD M,  
#” instruction. (See Figure 29)  
Figure 27: HALT Register Definition  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
x
x
x
x
x
x
EIDLE  
EHALT  
Figure 28: Recommended HALT Flow  
Figure 29: Recommended IDLE Flow  
Normal Mode  
Normal Mode  
LD HALT, #01h  
LD  
HALT, #01H  
Timer0  
Overflow  
Multi-Input  
Halt  
IDLE Mode  
Wakeup  
Multi-Input  
Wakeup  
LD PMC, #00H  
LD PMC, #00h  
Resume Normal  
Mode  
Resume  
Normal Mode  
27  
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ACE8001 Product Family Rev. B.2  
Ordering Information  
Core Max.#  
Program  
Operating  
Type  
I/Os Memory Size Voltage Range Temperature Range  
Package  
0 to -40 to -40 to 8-pin 8-pin  
Tape  
and  
1.8 –  
2.2 –  
Part Number  
ACE8001M8  
0
1
X
X
X
X
X
X
X
X
X
X
X
X
2
6
X
X
X
X
X
X
X
X
X
X
X
X
1K  
X
X
X
X
X
X
X
X
X
X
X
X
2K  
5.5V  
5.5V  
70°C +85C +125°C SOIC TSSOP Reel  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE8001M8X  
ACE8001MT8  
ACE8001MT8X  
ACE8001EM8  
ACE8001EM8X  
ACE8001EMT8  
ACE8001EMT8X  
ACE8000M8  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE8000M8X  
ACE8000EM8  
ACE8000EM8X  
X
X
28  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.189 - 0.197  
(4.800 - 5.004)  
8
7
6
5
0.228 - 0.244  
(5.791 - 6.198)  
1
2
3
4
Lead #1  
IDENT  
0.150 - 0.157  
0.053 - 0.069  
(1.346 - 1.753)  
(3.810 - 3.988)  
0.010 - 0.020  
(0.254 - 0.508)  
0.004 - 0.010  
(0.102 - 0.254)  
x 45°  
8° Max, Typ.  
All leads  
Seating  
Plane  
0.004  
(0.102)  
All lead tips  
0.0075 - 0.0098  
(0.190 - 0.249)  
Typ. All Leads  
0.014  
(0.356)  
0.016 - 0.050  
(0.406 - 1.270)  
Typ. All Leads  
0.050  
(1.270)  
Typ  
0.014 - 0.020  
Typ.  
(0.356 - 0.508)  
Molded Small Out-Line Package (M8)  
Order Number ACE8001M8/ACE8001EM8/ACE8000M8/ACE8000EM8  
Package Number M08A  
29  
www.fairchildsemi.com  
ACE8001 Product Family Rev. B.2  
Physical Dimensions inches (millimeters) unless otherwise noted  
0.114 - 0.122  
(2.90 - 3.10)  
8
5
(7.72) Typ  
(4.16) Typ  
0.169 - 0.177  
(4.30 - 4.50)  
0.246 - 0.256  
(6.25 - 6.5)  
(1.78) Typ  
(0.42) Typ  
0.123 - 0.128  
(3.13 - 3.30)  
(0.65) Typ  
Land pattern recommendation  
1
4
Pin #1 IDENT  
0.0433  
Max  
(1.1)  
0.0035 - 0.0079  
See detail A  
0.002 - 0.006  
(0.05 - 0.15)  
0.0256 (0.65)  
Typ.  
Gage  
plane  
0.0075 - 0.0118  
(0.19 - 0.30)  
0°-8°  
DETAIL A  
Typ. Scale: 40X  
0.0075 - 0.0098  
(0.19 - 0.25)  
0.020 - 0.028  
(0.50 - 0.70)  
Seating  
plane  
Notes: Unless otherwise specified  
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93  
8-Pin Molded TSSOP (MT8)  
Order Number ACE8001MT8/ACE8001EMT8  
Package Number MTC08  
30  
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ACE8001 Product Family Rev. B.2  
ACEx Emulator Kit: Fairchild also offers a low cost real-time in-  
circuit emulator kit that includes:  
ACEx Development Tools  
General Information  
Emulator board  
Emulator software  
Assembler and Manuals  
Power supply  
Fairchild Semiconductor offers different possibilities to evaluate  
and emulate software written for ACEx.  
Simulator: Is a Windows program able to load, assemble, and  
debug ACEx programs. It is possible to place as many breakpoints  
as needed, trace the program execution in symbolic format, and  
program a device with the proper options. The ACEx Simulator is  
available free-of-charge and can be downloaded from Fairchild’s  
web site at www.fairchildsemi.com/products/micro  
DIP14 target cable  
PC cable  
The ACEx emulator allows for debugging the program code in a  
symbolic format. It is possible to place one breakpoint and  
watch various data locations. It also has built-in programming  
capability.  
Prototype Board Kits: Fairchild offer two solutions for the sim-  
plification of the breadboard operation so that ACEx Applica-  
tions can be quickly tested.  
1) ACEDEMO is can be used for general purpose applications  
2) ACETXRX for transmitting / receiving (RF, IR, RS232,  
RS485) applications.  
ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,  
buzzer, and a lamp with a small breadboard area.  
Ordering P/Ns  
Programming Adapters:  
DIP8 - ACEADAPTN  
DIP14 - ACEADAPTN14  
TSSOP8 - ACEADAPTMT8  
SO8 - ACEADAPTM8  
SO14 - ACEADAPTM  
Emulator Kit:  
ACEICE (110Vac)  
ACEICEEU (220Vac)  
Prototype Boards:  
ACEDEMO  
ACETXRX (315MHz)  
ACETXRXEU (433MHz)  
Life Support Policy  
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written  
approval of the President of Fairchild Semiconductor Corporation. As used herein:  
1. Life support devices or systems are devices or systems which,  
(a) are intended for surgical implant into the body, or (b) support  
or sustain life, and whose failure to perform, when properly used  
in accordance with instructions for use provided in the labeling,  
can be reasonably expected to result in a significant injury to the  
user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
Fairchild Semiconductor  
Americas  
Fairchild Semiconductor  
Europe  
Fairchild Semiconductor  
Hong Kong  
Fairchild Semiconductor  
Japan Ltd.  
Customer Response Center  
Tel. 1-888-522-5372  
Fax: +44 (0) 1793-856858  
8/F, Room 808, Empire Centre  
68 Mody Road, Tsimshatsui East  
Kowloon. Hong Kong  
Tel; +852-2722-8338  
Fax: +852-2722-8383  
4F, Natsume Bldg.  
Deutsch  
English  
Français  
Italiano  
Tel: +49 (0) 8141-6102-0  
Tel: +44 (0) 1793-856856  
Tel: +33 (0) 1-6930-3696  
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2-18-6, Yushima, Bunkyo-ku  
Tokyo, 113-0034 Japan  
Tel: 81-3-3818-8840  
Fax: 81-3-3818-8841  
31  
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ACE8001 Product Family Rev. B.2  

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 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001EM8

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001EM8X

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001EMT8

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001EMT8X

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001M8

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001M8X

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001MT8

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD

ACE8001MT8X

 ACE8001 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
FAIRCHILD
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