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CD4010CN

更新时间：2024-09-18 02:27:32
品牌：FAIRCHILD
描述：Hex Buffers (Non-Inverting)

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CD4010CN 概述

Hex Buffers (Non-Inverting) 六角缓冲器（非反相） 栅极

CD4010CN 规格参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.48
其他特性：DUAL SUPPLY HIGH TO LOW VOLTAGE TRANSLATOR系列：4000/14000/40000
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：19.305 mm负载电容（CL）：15 pF
逻辑集成电路类型：BUFFER功能数量：6
输入次数：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：OPEN-DRAIN封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/15 V
Prop。Delay @ Nom-Sup：100 ns传播延迟（tpd）：100 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：5.08 mm子类别：Gates
最大供电电压 (Vsup)：15 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

CD4010CN 数据手册

通过下载CD4010CN数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

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October 1987  
Revised June 2000  
CD4010C  
Hex Buffers (Non-Inverting)  
General Description  
Features  
The CD4010C hex buffers are monolithic complementary  
MOS (CMOS) integrated circuits. The N- and P-channel  
enhancement mode transistors provide a symmetrical cir-  
cuit with output swings essentially equal to the supply volt-  
age. This results in high noise immunity over a wide supply  
voltage range. No DC power other than that caused by  
leakage current is consumed during static conditions. All  
inputs are protected against static discharge. These gates  
may be used as hex buffers, CMOS to DTL or TTL inter-  
face or as CMOS current drivers. Conversion ranges are  
from 3V to 15V providing VCC ≤ VDD. The devices also  
■ Wide supply voltage range: 3.0V to 15V  
■ Low power: 100 nW (typ.)  
■ High noise immunity: 0.45 VDD (typ.)  
■ High current sinking: 8 mA (min.) at VO = 0.5V  
capability: and VDD = 10V  
Applications  
•
•
•
•
•
•
•
•
Automotive  
Data terminals  
Instrumentation  
Medical electronics  
Alarm system  
have buffered outputs which improve transfer characteris-  
tics by providing very high gain.  
Industrial controls  
Remote metering  
Computers  
Ordering Code:  
Order Number  
CD4010CM  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4010CN  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Schematic Diagram  
Pin Assignments for DIP and SOIC  
Hex COS/MOS to DTL or TTL  
converter (inverting).  
Connect VCC to DTL or TTL supply.  
Connect VDD to COS/MOS supply.  
Top View  
© 2000 Fairchild Semiconductor Corporation  
DS005945  
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 1)  
Voltage at Any Pin (Note 2)  
Operating Temperature Range  
Storage Temperature Range (TS)  
Power Dissipation (PD)  
Dual-In-Line  
V
SS − 0.3V to VSS +15.5V  
−45°C to +85°C  
−65°C to +150°C  
700 mW  
Note 1: “Absolute Maximum Ratings indicate limits beyond which damage  
Small Outline  
500 mW to the device may occur. Operating Ratings indicate conditions for which  
the device is functional, but do not guarantee specific performance limits.”  
Lead Temperature (TL)  
(Soldering, 10 seconds)  
Note 2: This device should not be connected to circuits with the power on  
260°C  
VSS + 3V to VSS + 15V  
because high transient voltage may cause permanent damage.  
Operating Range (VDD  
)
DC Electrical Characteristics  
Test Conditions  
(Volts)  
Limits  
Symbol  
Characteristics  
−40°C  
+25°C  
Typ  
0.03  
0.05  
0.15  
0.5  
0
+85°C  
Units  
VO  
VDD  
Min  
Max  
3
Min  
Max  
3
Min  
Max  
42  
ICC  
Quiescent Device  
5
10  
5
µA  
µA  
µW  
µW  
V
Current  
5
5
70  
PD  
Quiescent Device  
Dissipation/Package  
Output Voltage  
LOW Level  
15  
15  
210  
700  
0.05  
0.05  
10  
5
50  
50  
0.01  
0.01  
0.01  
0.01  
VOL  
VOH  
10  
5
0
V
HIGH Level  
4.99  
9.99  
4.99  
9.99  
5
4.95  
9.95  
V
10  
10  
V
Noise Immunity  
(All Inputs)  
VNL  
V
V
V
V
O ≥ 1.5  
O ≥ 3.0  
O ≥ 3.5  
O ≥ 7.0  
0.4  
5
10  
5
1.6  
3.2  
1.4  
2.9  
3.6  
9.6  
−1.5  
1.5  
3
2.25  
4.5  
1.4  
2.9  
1.5  
3
V
V
VNH  
1.5  
3
2.25  
4.5  
V
10  
5
V
Output Drive Current  
N-Channel (Note 3)  
P-Channel (Note 3)  
3
2.4  
6.4  
−1  
mA  
mA  
mA  
mA  
pA  
IDN  
IDP  
0.5  
10  
5
8
2.5  
−1.25  
−0.6  
9.5  
10  
−0.72  
−0.48  
IIN  
Input Current  
10  
Note 3: IDN and IDP are tested one output at a time.  
www.fairchildsemi.com  
2
AC Electrical Characteristics (Note 4)  
T = 25°c, CL= 15 pF, unless otherwise noted. Typical Temperature coefficient for all values of VDD= 0.3%/°C  
A
Test Conditions  
Limits  
VDD  
Symbol  
Characteristics  
Min  
Typ  
Max  
Units  
(Volts)  
tPHL  
Propagation Delay Time:  
V
CC = VDD  
5
—
—
—
15  
10  
10  
70  
40  
35  
tPLH  
HIGH-to-LOW Level (tPHL  
)
10  
ns  
V
V
V
DD = 10V  
CC = 5V  
LOW-to-HIGH Level (tPLH  
)
CC = VDD  
5
—
—
—
50  
25  
15  
100  
70  
10  
V
V
V
DD = 10V  
40  
ns  
ns  
ns  
pF  
CC = 5V  
tTHL  
tTLH  
Transition Time:  
CC = VDD  
5
10  
5
—
—
—
—
—
20  
16  
80  
50  
5
60  
50  
HIGH-to-LOW Level (tTHL  
)
LOW-to-HIGH Level (tTLH  
)
VCC = VDD  
160  
120  
—
10  
Input Capacitance (CI)  
Any Input  
Note 4: AC Parameters are guaranteed by DC correlated testing.  
Typical Application  
3
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
16-Line Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
Package Number M16A  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Package Number N16E  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
5
www.fairchildsemi.com  

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