CD4013BCSJX [FAIRCHILD]
Dual D-Type Flip-Flop ; 双D型触发器\n
| 型号： | CD4013BCSJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Flip-Flop
|
| 文件： | 总6页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
CD4013BC
Dual D-Type Flip-Flop
General Description
Features
The CD4013B dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent data, set, reset, and clock inputs
and “Q” and “Q” outputs. These devices can be used for
shift register applications, and by connecting “Q” output to
the data input, for counter and toggle applications. The
logic level present at the “D” input is transferred to the Q
output during the positive-going transition of the clock
pulse. Setting or resetting is independent of the clock and
is accomplished by a high level on the set or reset line
respectively.
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 VDD (typ.)
■ Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Applications
•
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Industrial electronics
Remote metering
Computers
Ordering Code:
Order Number
CD4013BCM
CD4013BCSJ
CD4013BCN
Package Number
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
M14D
N14A
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC and SOP
CL
D
R
S
Q
Q
(Note 1)
0
1
x
x
x
x
0
0
0
1
0
1
0
0
0
0
1
1
0
1
Q
0
1
1
1
0
Q
1
x
x
x
0
1
No Change
x = Don't Care Case
Note 1: Level Change
Top View
© 1999 Fairchild Semiconductor Corporation
DS005946.prf
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Schematic Diagrams
Logic Diagram
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2
Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions (Note 3)
DC Supply Voltage (VDD
Input Voltage (VIN
)
−0.5 VDC to +18 VDC
−0.5 VDC to VDD +0.5 VDC
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
Operating Temperature Range (TA)
)
+3 VDC to +15 VDC
0 VDC to VDD VDC
−40°C to +85°C
)
)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 3: V = 0V unless otherwise specified.
SS
260°C
DC Electrical Characteristics (Note 3)
−40°C
+25°C
+85°C
Symbol
Parameter
Conditions
= 5V, V = V or V
SS
Units
Min
Max
Min
Typ
Max
4.0
Min
Max
I
Quiescent Device
Current
V
V
V
4.0
8.0
30
60
µA
µA
µA
DD
DD
DD
DD
IN
DD
= 10V, V = V or V
8.0
IN
DD
SS
SS
= 15V, V = V or V
16.0
16.0
120
IN
DD
V
V
V
V
LOW Level
|I | < 1.0 µA
O
OL
OH
IL
Output Voltage
V
V
V
= 5V
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
= 10V
= 15V
HIGH Level
|I | < 1.0 µA
O
Output Voltage
V
V
V
= 5V
4.95
9.95
4.95
9.95
4.95
9.95
V
V
V
DD
DD
DD
= 10V
= 15V
14.95
14.95
14.95
LOW Level
|I | < 1.0 µA
O
Input Voltage
V
V
V
= 5V, V = 0.5V or 4.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
O
= 15V, V = 1.5V or 13.5V
O
HIGH Level
|I | < 1.0 µA
O
IH
Input Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5V, V = 0.5V or 4.5V
3.5
7.0
3.5
7.0
3.5
7.0
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
V
O
= 15V, V = 1.5V or 13.5V
11.0
0.52
1.3
11.0
0.44
1.1
11.0
0.36
0.9
V
O
I
I
I
LOW Level Output
Current (Note 4)
= 5V, V = 0.4V
0.88
2.25
8.8
mA
mA
mA
mA
mA
mA
µA
µA
OL
O
= 10V, V = 0.5V
O
= 15V, V = 1.5V
3.6
3.0
2.4
O
HIGH Level Output
Current (Note 4)
= 5V, V = 4.6V
−0.52
−1.3
−3.6
−0.44
−1.1
−3.0
−0.88
−2.25
−8.8
−0.36
−0.9
−2.4
OH
O
= 10V, V = 9.5V
O
= 15V, V = 13.5V
O
−5
Input Current
= 15V, V = 0V
−0.3
−10
−0.3
−1.0
IN
IN
−5
= 15V, V = 15V
0.3
10
0.3
1.0
IN
Note 4: I
and I are measured one output at a time.
OL
OH
3
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AC Electrical Characteristics (Note 5)
T
A = 25°C, CL = 50 pF, R = 200k, unless otherwise noted
L
Symbol
CLOCK OPERATION
, t
Parameter
Conditions
Min
Typ
Max
Units
t
Propagation Delay Time
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
200
80
350
160
120
200
100
80
ns
ns
PHL PLH
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
65
ns
t
, t
Transition Time
100
50
ns
THL TLH
= 10V
= 15V
= 5V
ns
40
ns
t
, t
Minimum Clock
Pulse Width
100
40
200
80
ns
WL WH
= 10V
= 15V
= 5V
ns
32
65
ns
t
, t
Maximum Clock Rise and
Fall Time
15
µs
RCL FCL
= 10V
= 15V
= 5V
10
µs
5
µs
t
Minimum Set-Up Time
20
15
40
ns
SU
= 10V
= 15V
= 5V
30
ns
12
25
ns
f
Maximum Clock
Frequency
2.5
6.2
7.6
5
MHz
MHz
MHz
CL
= 10V
= 15V
12.5
15.5
SET AND RESET OPERATION
t
,
Propagation Delay Time
V
V
V
V
V
V
= 5V
150
65
45
90
40
25
5
300
130
90
ns
ns
ns
ns
ns
ns
pF
PHL(R)
DD
DD
DD
DD
DD
DD
t
= 10V
= 15V
= 5V
PLH(S)
t
,
Minimum Set and
Reset Pulse Width
180
80
WH(R)
t
= 10V
= 15V
WH(S)
50
C
Average Input Capacitance
Any Input
7.5
IN
Note 5: AC Parameters are guaranteed by DC correlated testing.
Switching Time Waveforms
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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