CD4017BCMX [FAIRCHILD]
Johnson Counter ; 约翰逊计数器\n
| 型号： | CD4017BCMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Johnson Counter
|
| 文件： | 总7页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
CD4017BC • CD4022BC
Decade Counter/Divider with 10 Decoded Outputs •
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Description
The CD4017BC is a 5-stage divide-by-10 Johnson counter
Features
■ Wide supply voltage range: 3.0V to 15V
with 10 decoded outputs and a carry out bit.
■ High noise immunity: 0.45 VDD (typ.)
The CD4022BC is a 4-stage divide-by-8 Johnson counter
with 8 decoded outputs and a carry-out bit.
■ Low power Fan out of 2 driving 74L
TTL compatibility: or 1 driving 74LS
■ Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
These counters are cleared to their zero count by a logical
“1” on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable sig-
nal is in the logical “0” state.
■ Low power: 10 µW (typ.)
■ Fully static operation
The configuration of the CD4017BC and CD4022BC per-
mits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are nor-
mally in the logical “0” state and go to the logical “1” state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a full cycle for every 10/8 clock input cycles and
is used as a ripple carry signal to any succeeding stages.
Applications
•
•
•
•
•
•
Automotive
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering
Ordering Code:
Order Number
CD4017BCM
CD4017BCSJ
CD4017BCN
CD4022BCM
CD4022BCN
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M16D
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
M16A
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4017B
Pin Assignments for DIP and SOIC
CD4022B
Top View
Top View
© 1999 Fairchild Semiconductor Corporation
DS005950.prf
www.fairchildsemi.com
Logic Diagrams
CD4017B
Terminal No. 8 = GND
Terminal No. 16 = V
DD
CD4022B
Terminal No. 16 = V
DD
Terminal No. 8 = GND
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD
Input Voltage (VIN
)
−0.5 VDC to +18 VDC
−0.5 VDC to VDD +0.5 VDC
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
Operating Temperature Range (TA)
)
+3 VDC to +15 VDC
0 to VDD VDC
)
)
Storage Temperature (TS)
Power Dissipation (PD)
Dual-In-Line
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: V = 0V unless otherwise specified.
SS
260°C
DC Electrical Characteristics (Note 2)
−40°C
+25°
Typ
0.5
+85°C
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
20
Min
Max
I
Quiescent Device
V
V
V
= 5V
20
40
80
150
300
600
µA
µA
µA
DD
DD
DD
DD
Current
= 10V
= 15V
1.0
40
5.0
80
V
V
V
V
LOW Level
|I | < 1.0 µA
O
OL
OH
IL
Output Voltage
V
V
V
= 5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
= 10V
= 15V
HIGH Level
|I | < 1.0 µA
O
Output Voltage
V
V
V
= 5V
4.95
9.95
4.95
9.95
5
4.95
9.95
V
V
V
DD
DD
DD
= 10V
= 15V
10
15
14.95
14.95
14.95
LOW Level
|I | < 1.0 µA
O
Input Voltage
V
V
V
= 5V, V = 0.5V or 4.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
O
= 15V, V = 1.5V or 13.5V
O
HIGH Level
|I | < 1.0 µA
O
IH
Input Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5V, V = 0.5V or 4.5V
3.5
7.0
3.5
7.0
3.5
7.0
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
V
O
= 15V, V = 1.5V or 13.5V
11.0
0.52
1.3
11.0
0.44
1.1
11.0
0.36
0.9
V
O
I
I
I
LOW Level Output
Current (Note 3)
= 5V, V = 0.4V
0.88
2.25
8.8
mA
mA
mA
mA
mA
mA
µA
µA
OL
O
= 10V, V = 0.5V
O
= 15V, V = 1.5V
3.6
3.0
2.4
O
HIGH Level Output
Current (Note 3)
= 5V, V = 4.6V
−0.2
−0.5
−1.4
−0.16 −0.36
−0.12
−0.3
−1.0
OH
IN
O
= 10V, V = 9.5V
−0.4
−1.2
−0.9
−3.5
O
= 15V, V = 13.5V
O
−5
Input Current
= 15V, V = 0V
−0.3
−10
−0.3
−1.0
IN
−5
= 15V, V = 15V
0.3
10
0.3
1.0
IN
Note 3: I and I are tested one output at a time.
OL
OH
3
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AC Electrical Characteristics (Note 4)
T = 25°C, C = 50 pF, R = 200k, t
and t = 20 ns, unless otherwise specified
fCL
A
L
L
rCL
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCK OPERATION
t
t
Propagation Delay Time Carry Out Line
V
V
V
V
V
V
V
V
V
= 5V
415
160
130
240
85
800
320
250
480
170
140
1000
400
320
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL, PLH
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
Carry Out Line
= 10V
= 15V
= 5V
C = 15 pF
L
70
Decode Out Lines
500
200
160
= 10V
= 15V
t
, t
Transition Time Carry Out and Decode Out Lines
TLH THL
t
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
200
100
80
100
50
40
2
360
180
130
200
100
80
ns
ns
TLH
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
ns
t
ns
THL
= 10V
= 15V
= 5V
ns
ns
f
t
t
t
Maximum Clock Frequency
Minimum Clock Pulse Width
Clock Rise and Fall Time
Measured with
Respect to Carry
Output Line
1.0
2.5
3.0
MHz
MHz
MHz
ns
CL
= 10V
= 15V
= 5V
5
6
, t
125
45
35
250
90
70
20
15
5
WL WH
= 10V
= 15V
= 5V
ns
ns
, t
µs
rCL fCL
= 10V
= 15V
= 5V
µs
µs
Minimum Clock Inhibit Data Setup Time
Average Input Capacitance
120
40
32
5
240
80
65
7.5
ns
SU
= 10V
= 15V
ns
ns
C
pF
IN
Note 4: AC Parameters are guaranteed by DC correlated testing.
AC Electrical Characteristics (Note 4)
T
A = 25°C, CL = 50 pF, RL = 200k, t
and t = 20 ns, unless otherwise specified
rCL fCL
Symbol
RESET OPERATION
Parameter
Conditions
Min
Typ
Max
Units
t
Propagation Delay Time
Carry Out Line
PHL, tPLH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
415
160
130
240
85
800
320
250
480
170
140
1000
400
320
400
140
110
150
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
Carry Out Line
= 10V
= 15V
= 5V
C = 15 pF
L
70
Decode Out Lines
500
200
160
200
70
= 10V
= 15V
= 5V
t
t
Minimum Reset
Pulse Width
W
= 10V
= 15V
= 5V
55
Minimum Reset
Removal Time
75
REM
= 10V
= 15V
30
25
50
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4
Timing Diagrams
CD4017B
CD4022B
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-1, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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