CD4019BCMX [FAIRCHILD]
Quad 2-input OR Gate ; 四2输入或门\n
| 型号： | CD4019BCMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-input OR Gate
|
| 文件： | 总6页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
CD4019BC
Quad AND-OR Select Gate
General Description
Features
The CD4019BC is a complementary MOS quad AND-OR
select gate. Low power and high noise margin over a wide
voltage range is possible through implementation of N- and
P-channel enhancement mode transistors. These comple-
mentary MOS (CMOS) transistors provide the building
blocks for the 4 “AND-OR select” gate configurations, each
consisting of two 2-input AND gates driving a single 2-input
OR gate. Selection is accomplished by control bits KA and
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 VDD (typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Applications
•
•
•
•
AND-OR select gating
KB. All inputs are protected against static discharge dam-
age.
Shift-right/shift-left registers
True/complement selection
AND/OR/EXCLUSIVE-OR selection
Ordering Code:
Order Number
CD4019BCM
CD4019BCSJ
CD4019BCN
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M16D
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005952.prf
www.fairchildsemi.com
Schematic Diagram
Schematic diagram for 1 of 4 identical stages
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operation
Conditions (Note 2)
Supply Voltage (VDD
)
−0.5V to +18V
−0.5V to VDD +0.5V
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
Operating Temperature Range (TA)
)
+3V to +15V
0V to VDD
−40°C to +85°C
Input Voltage (VIN
)
)
V
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: V = 0V unless otherwise specified.
SS
260°C
DC Electrical Characteristics (Note 3)
−40°C
+25°C
Typ
+85°C
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
Min
Max
I
Quiescent Device
Current
V
V
V
= 5V
1
2
4
0.03
0.05
0.07
1
2
4
7.5
15
30
µA
µA
µA
DD
DD
DD
DD
= 10V
= 15V
V
LOW Level
|I | < 1 µA
O
OL
Output Voltage
V
V
V
= 5V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
= 10V
= 15V
V
HIGH Level
|I | < 1 µA
O
OH
Output Voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
4.95
9.95
4.95
9.95
5
10
15
2
4.95
9.95
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
14.95
14.95
14.95
V
V
V
LOW Level
= 5V, V = 0.5V or 4.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
IL
O
Input Voltage
= 10V, V = 1.0V or 9.0V
4
V
O
= 15V, V = 1.5V or 13.5V
6
V
O
HIGH Level
= 5V, V = 0.5V or 4.5V
3.5
7.0
3.5
7.0
3
3.5
7.0
V
IH
O
Input Voltage
= 10V, V = 1.0V or 9.0V
6
V
O
= 15V, V = 1.5V or 13.5V
11.0
0.52
1.3
11.0
0.44
1.1
9
11.0
0.36
0.9
V
O
I
LOW Level Output
Current (Note 4)
= 5V, V = 0.4V
1
mA
mA
mA
mA
mA
mA
µA
µA
OL
O
= 10V, V = 0.5V
2.5
10
−0.4
−1.0
−3.0
O
= 15V, V = 1.5V
3.6
3.0
2.4
O
I
HIGH Level Output
Current (Note 4)
= 5V, V = 4.6V
−0.2
−0.5
−1.4
−0.16
−0.4
−1.2
−0.12
−0.3
−1.0
OH
O
= 10V, V = 9.5V
O
= 15V, V = 13.5V
O
−5
I
Input Current
= 15V, V = 0V
−0.30
−10
−0.30
−1.0
IN
IN
−5
= 15V, V = 15V
0.30
10
0.30
1.0
IN
Note 3: V = 0V unless otherwise specified.
SS
Note 4: I
and I are tested one output at a time.
OL
OH
3
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AC Electrical Characteristics (Note 5)
T
A = 25°C, CL = 50 pF, R = 200k, unless otherwise specified
L
Symbol
Parameter
Propagation Delay,
Input to Output
Conditions
Min
Typ
100
50
Max
300
120
100
200
100
80
Units
ns
t
,
V
V
V
V
V
V
V
V
V
= 5V
PHL
DD
DD
DD
DD
DD
DD
DD
DD
DD
t
= 10V
= 15V
= 5V
ns
PLH
45
ns
t
HIGH-to-LOW Level
Transition Time
100
50
ns
THL
= 10V
= 15V
= 5V
ns
40
ns
t
LOW-to-HIGH Level
Transition Time
150
70
300
140
100
7.5
ns
TLH
= 10V
= 15V
ns
50
ns
C
Input Capacitance
All A and B Inputs
and K Inputs
5
pF
pF
IN
K
10
15
A
B
Note 5: AC Parameters are guaranteed by DC correlated testing.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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