CD4023 [FAIRCHILD]
Buffered Triple 3-Input NAND Gate; 缓冲的三重3输入与非门
| 型号： | CD4023 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Buffered Triple 3-Input NAND Gate |
| 文件： | 总6页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised August 2000
CD4023BC
Buffered Triple 3-Input NAND Gate
General Description
Features
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors. They have equal
source and sink current capabilities and conform to stan-
dard B series output drive. The devices also have buffered
outputs which improve transfer characteristics by providing
very high gain. All inputs are protected against static dis-
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 VDD (typ)
■ Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
■ 5V–10V–15V parametric ratings
■ Symmetrical output characteristics
charge with diodes to VDD and VSS
.
■ Maximum input leakage 1 µA at 15V over full
temperature range
Ordering Code:
Order Number Package Number
Package Description
CD4023BCM
CD4023BCS
CD4023BCN
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Connection Diagram
Block Diagram
1
/
3 Device Shown
*All Inputs Protected by Standard CMOS Input Protection Circuit.
Top View
© 2000 Fairchild Semiconductor Corporation
DS005956
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
DC Supply Voltage (VDD
)
−0.5 VDC to +18 VDC
−0.5 VDC to VDD+0.5 VDC
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
Operating Temperature Range (TA)
)
5 VDC to 15 VDC
0 VDC to VDD VDC
−40°C to +85°C
Input Voltage (VIN
)
)
Storage Temp. Range (TS)
Power Dissipation (PD)
Dual-In-Line
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
260°C
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 3)
−40°C
+25°C
Typ
0.004
0.005
0.006
0
+85°C
Symbol
IDD
Parameter
Conditions
Units
Min
Typ
Min
Max
1.0
Min
Max
Quiescent Device Current
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD = 5V
1.0
2.0
7.5
15
DD = 10V
DD = 15V
DD = 5V
2.0
µA
4.0
4.0
30
VOL
VOH
VIL
LOW Level Output Voltage
HIGH Level Output Voltage
LOW Level Input Voltage
HIGH Level Input Voltage
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
DD = 10V
DD = 15V
DD = 5V
0
V
V
0
4.95
9.95
4.95
9.95
5
4.95
9.95
DD = 10V
DD = 15V
10
14.95
14.95
15
14.95
DD=5V, VO=4.5V
1.5
3.0
4.0
2
1.5
3.0
4.0
1.5
3.0
4.0
DD=10V, VO=9.0V
DD=15V, VO=13.5V
DD=5V, VO=0.5V
|IO|<1µA
|IO|<1µA
4
V
6
VIH
IOL
IOH
IIN
3.5
7.0
3.5
7.0
3
3.5
7.0
DD=10V, VO=1.0V
DD=15V, VO=1.5V
DD=5V, VO = 0.4V
DD = 10V, VO = 0.5V
DD = 15V, VO = 1.5V
DD = 5V, VO = 4.6V
DD = 10V, VO = 9.5V
DD = 15V, VO = 13.5V
DD = 15V, VIN = 0V
DD = 15V, VIN = 15V
6
V
11.0
0.52
1.3
11.0
0.44
1.1
9
11.0
0.36
0.90
2.4
LOW Level Output Current
(Note 4)
0.88
2.2
8
mA
3.6
3.0
HIGH Level Output Current
(Note 4)
−0.52
−1.3
−3.6
−0.44
−1.1
−3.0
−0.88
−2.2
−8
−0.36
−0.90
−2.4
mA
−5
Input Current
−0.3
−10
−0.3
−1.0
µA
−5
0.3
10
0.3
1.0
Note 3: VSS = 0V unless otherwise specified.
Note 4: IOH and IOL are tested one output at a time.
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2
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise specified
Symbol
tPHL
Parameter
Conditions
DD = 5V
Min
Typ
130
60
40
110
50
35
90
50
40
5
Max
250
100
70
Units
Propagation Delay, HIGH-to-LOW Level
V
V
DD = 10V
DD = 15V
ns
V
tPLH
Propagation Delay, LOW-to-HIGH Level
Transition Time
V
DD = 5V
DD = 10V
DD = 15V
250
100
70
V
V
ns
ns
tTHL
,
V
DD = 5V
DD = 10V
DD = 15V
200
100
80
tTLH
V
V
CIN
Average Input Capacitance
Any Input
Any Gate
7.5
pF
pF
CPD
Power Dissipation Capacity (Note 6)
17
Note 5: AC Parameters are guaranteed by DC correlated testing.
Note 6: CPD determines the no load AC power consumption of any CMOS device.
For complete explanation, see Family Characteristics Application Note AN-90.
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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