CD4503BCN-NL [FAIRCHILD]
Bus Driver, 2-Func, 6-Bit, True Output, CMOS, PDIP16,;型号: | CD4503BCN-NL |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Bus Driver, 2-Func, 6-Bit, True Output, CMOS, PDIP16, 驱动 光电二极管 逻辑集成电路 |
文件: | 总6页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
October 1987
Revised January 2004
CD4503BC
Hex Non-Inverting 3-STATE Buffer
General Description
Features
The CD4503BC is a hex non-inverting 3-STATE buffer with
high output current sink and source capability. 3-STATE
outputs make it useful in bus-oriented applications. Two
separate disable inputs are provided. Buffers 1 through 4
are controlled by the disable 4 input. Buffers 5 and 6 are
controlled by the disable 2 input. A high level on either dis-
able input will cause those gates on its control line to go
into a high impedance state.
■ Wide supply voltage range: 3.0 VDC to 18 VDC
■ 3-STATE outputs
■ Symmetrical turn on/turn off delays
■ Symmetrical output rise and fall times
■ Pin-for-pin replacement for MM80C97 and MC14503
Ordering Code:
Order Number Package Number
Package Description
CD4503BCM
CD4503BCN
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Schematic Diagram
Truth Table
Top View
In
Disable
Out
Input
0
1
X
0
0
1
0
1
3-STATE
X = Don’t Care
© 2004 Fairchild Semiconductor Corporation
DS005989
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VDD
Input Voltage (VIN
)
−0.5V to +18V
−0.5V to +0.5V
−65°C to +150°C
Supply Voltage (VDD
)
+3V to +15V
)
Operating Temperature Range (TA)
−55°C to +125°C
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics (Note 2)
−55°C
+25°C
+125°C
Symbol
IDD
Parameter
Conditions
Units
Min
Max
Min
Typ
Max
Min
Max
Quiescent Device
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD = 5V,
1
2
4
1
30
Current
IN = VDD or VSS
DD = 10V,
2
4
60
µA
IN = VDD or VSS
DD = 15V,
120
IN = VDD or VSS
IN = VDD or 0
DD = 5V
VOL
VOH
VIL
LOW Level
Output Voltage
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
DD = 10V
V
V
DD = 15V
HIGH Level
IN = V DD or 0
DD = 5V
Output Voltage
4.95
9.95
4.95
9.95
5
4.95
9.95
DD = 10V
10
DD = 15V
14.95
14.95
15
14.95
LOW Level
DD = 5V,
1.5
3.0
4.0
2.25
1.5
3.0
4.0
1.5
3.0
4.0
Input Voltage
O = 4.5V or 0.5V
DD = 10V,
4.50
6.75
2.75
5.5
V
O = 9.0V or 1.0V
DD = 15V,
O = 13.5V or 1.5V
DD = 5V,
VIH
HIGH Level
3.5
7.0
3.5
7.0
3.5
7.0
Input Voltage
O = 0.5V or 4.5V
DD = 10V,
V
O = 1.0V or 9.0V
DD = 15V,
11.0
11.0
8.25
11.0
O = 1.5V or 13.5V
DD = 4.5V, VOL = 0.4V
DD = 5.0V, VOL = 0.4V
DD = 10V, V OL = 0.5V
DD = 15V, VOL = 1.5V
DD = 5V, VOH = 4.6V
DD = 10V, VOH = 9.5V
DD = 15V, VOH = 13.5V
DD = 15V
IOL
LOW Level Output
Current
2.8
2.3
2.4
2.55
2.75
7.00
1.60
1.75
4.45
11.30
−0.7
−1.8
−4.8
3.0
mA
mA
7.85
6.35
19.95
−1.28
−3.20
−8.20
16.10 25.00
−1.02 −1.76
−2.60 −4.5
−6.80 −17.6
IOH
HIGH Level Output
Current
−4
IOZ
IIN
3-STATE Leakage Current
Input Current
±0.1
±0.1
±10
±0.1
±0.1
±1.0
±1.0
µA
µA
−4
DD = 15V
±10
Note 3: IOH and IOL are tested one output at a time.
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2
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200 kΩ, Input tr = tf = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
75
35
25
80
40
35
95
40
35
45
23
18
45
23
18
Max
100
40
Units
tPHL, tPLH
tPLZ, tPHZ
tPZL, tPZH
tTLH
Propagation Delay Time
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD = 5V
DD = 10V
DD = 15V
DD = 5V
ns
30
Propagation Delay Time,
Logical Level to HIGH
Impedance State
125
90
DD = 10V
DD = 15V
DD = 5V
ns
ns
ns
ns
70
Propagation Delay Time,
High Impedance State to
Logical Level
175
80
DD = 10V
DD = 15V
DD = 5V
70
Output Rise Time
80
DD = 10V
DD = 15V
DD = 5V
40
35
tTHL
Output Fall Time
80
DD = 10V
DD = 15V
40
35
Note 4: AC Parameters are guaranteed by DC correlated testing.
3
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AC Test Circuits and Switching Time Waveforms
tPHL, tPLH
CMOS to CMOS
t
PHZ and tPZH
tPLZ and tPZL
tPHZ
tPLZ
tPZH
tPZL
Note: Delays measured with input tr, tf ≤ 20 ns.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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