CD4538BCN_NL [FAIRCHILD]
Monostable Multivibrator, 4000/14000/40000 Series, 2-Func, CMOS, PDIP16, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-16;
| 型号： | CD4538BCN_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Monostable Multivibrator, 4000/14000/40000 Series, 2-Func, CMOS, PDIP16, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-16 |
| 文件： | 总11页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
CD4538BC
Dual Precision Monostable
General Description
Features
The CD4538BC is a dual, precision monostable multivibra-
tor with independent trigger and reset controls. The device
is retriggerable and resettable, and the control inputs are
internally latched. Two trigger inputs are provided to allow
either rising or falling edge triggering. The reset inputs are
active LOW and prevent triggering while active. Precise
control of output pulse-width has been achieved using lin-
ear CMOS techniques. The pulse duration and accuracy
are determined by external components RX and CX. The
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 VCC (typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
■ New formula: PWOUT = RC (PW in seconds, R in Ohms,
C in Farads)
■ ±1.0% pulse-width variation from part to part (typ.)
■ Wide pulse-width range: 1 µs to ∞
■ Separate latched reset inputs
device does not allow the timing capacitor to discharge
through the timing pin on power-down condition. For this
reason, no external protection resistor is required in series
with the timing pin. Input protection from static discharge is
provided on all pins.
■ Symmetrical output sink and source capability
■ Low standby current: 5 nA (typ.) @ 5 VDC
■ Pin compatible to CD4528BC
Ordering Code:
Order Number Package Number
Package Description
CD4538BCM
CD4538BCWM
CD4538BCN
M16A
M16B
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Inputs
Outputs
Clear
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↓
↑
H
H = HIGH Level
L = LOW Level
↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant
Top View
© 1999 Fairchild Semiconductor Corporation
DS006000.prf
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Block Diagram
R
V
and C are External Components
X
X
= Pin 16
= Pin 8
DD
V
SS
Logic Diagram
FIGURE 1.
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2
Theory of Operation
FIGURE 2.
Thus, propagation delay from trigger to Q is independent of
Trigger Operation
the value of CX, RX, or the duty cycle of the input wave-
The block diagram of the CD4538BC is shown in Figure 1,
form.
with circuit operation following.
As shown in Figure 1 and Figure 2, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
Retrigger Operation
The CD4538BC is retriggered if a valid trigger occurs(3) fol-
lowed by another valid trigger(4) before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin 2 or 14 has begun to rise
from VREF1, but has not yet reached VREF2, will cause an
to VDD. When the trigger input A goes from VSS to VDD
(while inputs B and CD are held to VDD) a valid trigger is
recognized, which turns on comparator C1 and N-Channel
transistor N1(1). At the same time the output latch is set.
increase in output pulse width T. When a valid retrigger is
initiated(4), the voltage at T2 will again drop to VREF1 before
progressing along the RC charging curve toward VDD. The
With transistor N1 on, the capacitor CX rapidly discharges
toward VSS until VREF1 is reached. At this point the output
of comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time com-
parator C2 turns on. With transistor N1 off, the capacitor CX
Q output will remain high until time T, after the last valid
retrigger.
begins to charge through the timing resistor, RX, toward
VDD. When the voltage across CX equals VREF2, compara-
Reset Operation
The CD4538BC may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on CD sets the reset latch and causes the capacitor to be
tor C2 changes state causing the output latch to reset (Q
goes low) while at the same time disabling comparator C2.
This ends the timing cycle with the monostable in the qui-
escent state, waiting for the next trigger.
fast charged to VDD by turning on transistor Q1(5). When
A valid trigger is also recognized when trigger input B goes
the voltage on the capacitor reaches VREF2, the reset latch
from VDD to VSS (while input A is at VSS and input CD is at
(2)
will clear and then be ready to accept another pulse. If the
CD input is held low, any trigger inputs that occur will be
VDD
) .
It should be noted that in the quiescent state CX is fully
charged to VDD, causing the current through resistor RX to
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the CD input, the output pulse T can be
be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the CD4538BC is that the output latch is set via
the input trigger without regard to the capacitor voltage.
made significantly shorter than the minimum pulse width
specification.
3
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FIGURE 3. Retriggerable Monostables Circuitry
FIGURE 4. Non-Retriggerable Monostables Circuitry
FIGURE 5. Connection of Unused Sections
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4
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD
)
−0.5 to +18 VDC
−0.5V to VDD + 0.5 VDC
−65°C to +150°C
DC Supply Voltage (VDD
Input Voltage (VIN
Operating Temperature Range (TA)
)
3 to 15 VDC
0 to VDD VDC
Input Voltage (VIN
)
)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
700 mW
500 mW
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
Note 2: V = 0V unless otherwise specified.
SS
260°C
DC Electrical Characteristics (Note 2)
−40°C
+25°C
Typ
0.005
0.010
0.015
0
+85°C
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
20
Min
Max
I
Quiescent
V
V
V
V
V
V
V
V
V
= 5V
V
= V
20
40
150
300
600
0.05
0.05
0.05
µA
µA
µA
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
IH
DD
Device Current
= 10V
V
= V
40
IL
SS
= 15V All Outputs Open
80
80
V
V
V
LOW Level
= 5V
|I | < 1 µA
0.05
0.05
0.05
0.05
0.05
0.05
OL
OH
IL
O
Output Voltage
= 10V
= 15V
= 5V
V
= V , V = V
0
V
IH
DD
IL
SS
SS
0
V
HIGH Level
|I | < 1 µA
4.95
9.95
4.95
9.95
5
4.95
9.95
V
O
Output Voltage
= 10V
= 15V
V
= V , V = V
10
V
IH
DD
IL
14.95
14.95
15
14.95
V
LOW Level
|I | < 1 µA
O
Input Voltage
V
V
V
= 5V, V = 0.5V or 4.5V
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
O
= 15V, V = 1.5V or 13.5V
O
V
HIGH Level
|I | < 1 µA
O
IH
Input Voltage
V
V
V
V
V
V
V
V
V
V
= 5V, V = 0.5V or 4.5V
3.5
7.0
3.5
7.0
2.75
5.50
8.25
0.88
2.25
8.8
3.5
7.0
V
DD
DD
DD
DD
DD
O
= 10V, V = 1.0V or 9.0V
V
O
= 15V, V = 1.5V or 13.5V
11.0
0.52
1.3
11.0
0.44
1.1
11.0
0.36
0.9
V
O
I
I
LOW Level
Output Current
(Note 3)
= 5V, V = 0.4V
V
V
= V
mA
mA
mA
mA
mA
mA
µA
OL
O
IH
IL
DD
= 10V, V = 0.5V
= V
O
SS
= 15V, V = 1.5V
3.6
3.0
2.4
D
O
HIGH Level
Output Current
(Note 3)
= 5V, V = 4.6V
−0.52
−1.3
−3.6
−0.44 −0.88
−1.1 −2.25
−0.36
−0.9
−2.4
OH
IN
DD
DD
O
= 10V, V = 9.5V
V
= V
O
IL
SS
= 15V, V = 13.5V
−3.0
−8.8
D
O
−5
I
I
Input Current,
Pin 2 or 14
Input Current
Other Inputs
= 15V, V = 0V or 15V
±0.02
±0.3
±10
±0.05
±0.3
±0.5
±1.0
DD
IN
−5
V
= 15V, V = 0V or 15V
±10
µA
IN
DD
IN
Note 3: I
and I are tested one output at a time.
OL
OH
5
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AC Electrical Characteristics (Note 4)
T
A = 25°C, CL = 50 pF, and t = t = 20 ns unless otherwise specified
r
f
Symbol
, t
Parameter
Conditions
Min
Typ
Max
Units
t
Output Transition Time
Propagation Delay Time
V
V
V
= 5V
100
50
200
100
80
ns
ns
ns
TLH THL
DD
DD
DD
= 10V
= 15V
40
t
, t
Trigger Operation—
A or B to Q or Q
PLH PHL
V
V
V
= 5V
300
150
100
600
300
220
ns
ns
ns
DD
DD
DD
= 10V
= 15V
Reset Operation—
C
to Q or Q
D
V
V
V
V
V
V
V
V
V
= 5V
250
125
95
500
250
190
70
60
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
µs
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 10V
= 15V
= 5V
t
, t
Minimum Input Pulse Width
35
WL WH
A, B, or C
= 10V
= 15V
= 5V
30
D
25
t
Minimum Retrigger Time
Input Capacitance
RR
= 10V
= 15V
0
0
0
C
Pin 2 or 14
10
5
IN
Other Inputs
7.5
PW
V
= 5V
208
226
244
R
= 100 kΩ
Output Pulse Width (Q or Q)
(Note: For Typical Distribution,
see Figure 6)
OUT
DD
X
X
C
= 0.002 µF
V
V
V
V
V
V
V
V
V
V
V
= 10V
= 15V
= 5V
211
216
230
235
9.60
9.80
10.00
0.95
0.97
0.99
±1
248
254
µs
µs
ms
ms
ms
s
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
R
C
= 100 kΩ
= 0.1 µF
8.83
9.02
9.20
0.87
0.89
0.91
10.37
10.59
10.80
1.03
1.05
1.07
X
= 10V
= 15V
= 5V
X
R
C
= 100 kΩ
= 10.0 µF
X
= 10V
= 15V
= 5V
s
X
s
Pulse Width Match between
Circuits in the Same Package
R
C
= 100 kΩ
= 0.1 µF
%
%
%
X
= 10V
= 15V
±1
X
C
= 0.1 µF, R = 100 kΩ
±1
X
X
Operating Conditions
R
C
External Timing Resistance
External Timing Capacitance
5.0
0
(Note 5)
No Limit
kΩ
X
X
pF
Note 4: AC parameters are guaranteed by DC correlated testing.
Note 5: The maximum usable resistance R is a function of the leakage of the Capacitor C , leakage of the CD4538BC, and leakage due to board layout,
X
X
surface resistance, etc.
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6
Typical Applications
FIGURE 6. Typical Normalized Distribution of Units
for Output Pulse Width
FIGURE 9. Typical Pulse Width Error
Versus Temperature
FIGURE 7. Typical Pulse Width Variation as a
Function of Supply Voltage VDD
FIGURE 10. Typical Pulse Width Error
Versus Temperature
FIGURE 8. Typical Total Supply Current Versus
Output Duty Cycle, RX = 100 kΩ, CL = 50 pF,
FIGURE 11. Typical Pulse Width Versus
Timing RC Product
C
X = 100 pF, One Monostable Switching Only
7
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Test Circuits and Waveforms
FIGURE 12. Switching Test Waveforms
*C = 50 pF
L
Input Connections
Characteristics
PLH, tPHL, tTLH, tTHL
CD
A
B
t
VDD
PG1
VDD
PWOUT, tWH, tWL
tPLH, tPHL, tTLH, tTHL
PWOUT, tWH, tWL
VDD
VSS
PG2
tPLH(R), tPHL(R)
,
PG3 PG1 PG2
tWH, tWL
*Includes capacitance of probes, wiring, and fixture parasitic
Note: Switching test waveforms for PG1, PG2, PG3 are shown in Figure 12.
FIGURE 13. Switching Test Circuit
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8
R
C
C
= R ′ = 100 kΩ
X
X
X
1
= C ′ = 100 pF
X
= C = 0.1 µF
2
Duty Cycle = 50%
FIGURE 14. Power Dissipation Test
Circuit and Waveforms
9
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M16B
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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