DM74ALS573B [FAIRCHILD]
Extended Temperature Octal D-Type Transparent Latch; 扩展温度八路D型透明锁存器
| 型号： | DM74ALS573B |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Extended Temperature Octal D-Type Transparent Latch |
| 文件： | 总7页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1984
Revised February 2000
DM74ALS573B
Extended Temperature Octal D-Type Transparent Latch
with 3-STATE Outputs
General Description
Features
■ Switching specifications at 50 pF
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
■ Switching specifications guaranteed over full tempera-
ture and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally equivalent with DM74LS373
■ Improved AC performance over DM74LS373 at approxi-
mately half the power
The eight latches of the DM74ALS573B are transparent D-
type latches. While the enable (G) is HIGH the Q outputs
will follow the data (D) inputs. When the enable is taken
LOW the output will be latched at the level of the data that
was set UP.
■ 3-STATE buffer-type outputs drive bus lines directly
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Ordering Code:
Order Number
DM74ALS573BWM
DM74ALS573BSJ
DM74ALS573BN
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M20D
N20A
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006226
www.fairchildsemi.com
Function Table
Logic Diagram
Output
Enable
D
Output
Control
G
H
H
L
Q
H
L
L
H
L
L
L
X
X
Q0
Z
H
X
L = LOW State
H = HIGH State
X = Don’t Care
Z = High Impedance State
Q
= Previous Condition of Q
0
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2
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
7V
Input Voltage
Voltage Applied to Disabled Output
5.5V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Operating Free Air Temperature Range
Storage Temperature Range
Typical θJA
0°C to +70°C
−65°C to +150°C
N Package
56.0°C/W
75.0°C/W
M Package
Recommended Operating Conditions
Symbol
Parameter
Min
4.5
2
Nom
Max
Units
V
VCC
VIH
VIL
IOH
IOL
tW
Supply Voltage
5
5.5
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Width of Enable Pulse, HIGH
Data Setup Time (Note 2)
Data Hold Time (Note 2)
V
0.8
−2.6
24
V
mA
mA
ns
10
10↓
7↓
tSU
tH
ns
ns
TA
Free Air Operating Temperature
0
70
°C
Note 2: The (↓) arrow indicates the negative edge of the enable is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, T = 25°C.
A
Symbol
Parameter
Conditions
= 4.5V, I = −18 mA
Min
Typ
Max
Units
V
V
Input Clamp Voltage
HIGH Level
V
V
V
V
V
V
−1.2
V
V
IK
CC
CC
I
= 4.5V
OH
I
= Max
2.4
3.2
OH
Output Voltage
= V Max
IL
IL
= 4.5V to 5.5V
= 4.5V
I
I
I
= −400 µA
= 12 mA
= 24 mA
V
− 2
V
V
V
CC
CC
OH
OL
OL
CC
V
LOW Level
0.25
0.35
0.4
0.5
OL
Output Voltage
= 2V
IH
I
Input Current @ Maximum
Input Voltage
I
V
= 5.5V, V = 7V
0.1
mA
CC
IH
I
I
I
I
HIGH Level Input Current
LOW Level Input Current
Output Drive Current
OFF-State Output Current
HIGH Level Voltage Applied
OFF-State Output Current
LOW Level Voltage Applied
Supply Current
V
V
V
V
V
V
V
V
= 5.5V, V = 2.7V
20
µA
mA
mA
IH
CC
CC
CC
CC
IH
= 5.5V, V = 0.4V
−0.1
−112
IL
IL
= 5.5V, V = 2.25V
−30
O
O
= 5.5V, V = 2V
OZH
IH
20
µA
µA
= 2.7V
O
I
I
= 5.5V, V = 2V
IH
OZL
CC
CC
−20
= 0.4V
O
= 5.5V
Outputs HIGH
Outputs LOW
10
15
17
24
27
mA
mA
mA
CC
Outputs OPEN
Outputs Disabled
15.5
3
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Switching Characteristics
over recommended operating free air temperature range.
Symbol
Parameter
Conditions
From
To
Min
Max
Units
t
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
V
R
C
= 4.5V to 5.5V
PLH
CC
Data
Any Q
2
14
ns
= 500Ω
= 50 pF
L
L
t
PHL
Data
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
2
6
6
3
4
1
1
14
20
19
18
18
10
15
ns
ns
ns
ns
ns
ns
ns
t
PLH
Enable
Enable
t
PHL
t
Output
Control
Output
Control
Output
Control
Output
Control
PZH
to HIGH Level Output
Output Enable Time
t
PZL
to LOW Level Output
t
Output Disable Time
PHZ
from HIGH Level Output
Output Disable Time
t
PLZ
from LOW Level Output
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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